str755fvx STMicroelectronics, str755fvx Datasheet
str755fvx
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str755fvx Summary of contents
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ARM7TDMI-S™ 32-bit MCU with Flash, SMI, 3 std 16-bit timers, PWM timer, fast 10-bit ADC, I2C, UART, SSP, USB and CAN Core I – ARM7TDMI-S 32-bit RISC CPU – 54 DMIPS @ 60 MHz Memories I – 256 ...
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Contents Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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STR750F 3.3.12 10-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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... RWW -40 to +85°C / -40 to +105°C (see 3 UARTs, 2 SSPs, 1 I2C, 3 timers 1 PWM timer, 38 I/Os 13 Wake-up lines, 11 A/D Channels None USB 3. 3.3V T=LQFP64 10x10, H=LFBGA64 STR750F STR755FVx STR750FVx 16K Table 44 UARTs, 2 SSPs timers 1 PWM timer, 72 I/Os 15 Wake-up lines, 16 A/D Channels CAN ...
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STR750F 1.1 Overview The STR750 family includes devices in 2 package sizes: 64-pin and 100-pin. Both types have the following common features: ARM7TDMI-S core with embedded Flash & RAM TM STR750 family has an embedded ARM core and is therefore ...
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Introduction In SLOW mode, the AHB clock can be significantly decreased to reduce power consumption. The built-in Clock Controller also provides the 48 MHz USB clock directly without any extra oscillators or PLL. For instance, starting from the 4 MHz ...
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STR750F Low Power modes The STR750F supports 5 low power modes, SLOW, PCG, WFI, STOP and STANDBY. SLOW MODE: the system clock speed is reduced. Alternatively, the PLL and the main G oscillator can be stopped and the device is ...
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Introduction Timebase Timer (TB) The timebase timer is based on a 16-bit auto-reload counter and not connected to the I/O pins. It can be used for software triggering implement the scheduler of a real time operating system. Synchronizable ...
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STR750F High Speed Universal Asynch. Receiver Transmitter (UART) The three UART interfaces are able to communicate at speeds Mbit/s. They provide hardware management of the CTS and RTS signals and have LIN Master capability. To optimize ...
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Introduction 1.2 Block Diagram Figure 1. STR750 block diagram BOOT1, BOOT0 as AF TEST NJTRST JTDI JTCK JTMS JTDO as AF SCLK, MOSI MISO 15AF P0[31:0] P1[19:0] P2[19:0] 16AF VDDA_ADC VSSA_ADC 2xICAP, 2xOCMP as ...
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STR750F 2 Pin Description Figure 2. LQFP100 Pinout ADC_IN13 / P1.12 ADC_IN0 / TIM2_OC1/ P0.02 MCO / TIM0_TI1 / P0.01 BOOT0 / TIM0_OC1 / P0.00 TIM1_TI2 / P0.31 TIM1_OC2 / P0.30 ADC_IN8 / TIM1_TI1 / P0.29 TIM1_OC1 / P0.28 ADC_IN6 ...
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Pin Description Figure 3. LQFP64 Pinout ADC_IN13 / P1.12 ADC_IN0 / TIM2_OC1 / P0.02 MCO / TIM0_TI1 / P0.01 BOOT0 / TIM0_OC1 / P0.00 ADC_IN8 / TIM1_TI1 / P0.29 TIM1_OC1 / P0.28 UART1_TX / P0.21 UART1_RX / P0.20 JTMS / ...
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STR750F Table 3. LFBGA100 ball connections P0.03 P1.13 P1.14 B P1.12 P0.02 P0.01 C P0.31 P0. P0.29 P0. P0.28 P0.23 P0.22 F P2.03 P0.21 P0.20 G NJTRST P1.18 P1.19 H P0.13 P1.16 P1.17 ...
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Pin Description 2.0.1 Pin Description Table Legend / Abbreviations for Type: Input Levels: Inputs: Outputs: External Interrupts/wake-up lines: EITx 14/71 Table input output supply, All Inputs are LVTTL at V DD_IO ± at ...
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STR750F Port Reset State The reset state of the I/O ports is GPIO input floating. Exceptions are P1[19:16] and P0.13 which are configured as JTAG alternate functions: The JTAG inputs (JTDI, JTMS and JTDI) are configured as input floating and ...
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Pin Description Table 5. STR750F pin description (continued) Pin n° Pin Name P0.29 / TIM1_TI1 I/O / ADC_IN8 P0. I/O TIM1_OC1 TEST ...
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STR750F Table 5. STR750F pin description (continued) Pin n° Pin Name P0.11 / UART0_TX / I/O BOOT1 / SMI_CS2 P0. UART0_RX / I/O SMI_CS3 P0.09 / I2C_SDA ...
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Pin Description Table 5. STR750F pin description (continued) Pin n° Pin Name XT2 XT1 48 J10 31 G6 VSS_IO S 49 K10 32 G8 VSSA_PLL P2.15 I ...
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STR750F Table 5. STR750F pin description (continued) Pin n° Pin Name 71 C9 P2.11 I/O 72 B10 P2.10 I VSSA_ADC VSS_IO VREG_DIS I P0. ...
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Pin Description Table 5. STR750F pin description (continued) Pin n° Pin Name 94 D5 P1.01 / TIM0_TI2 I/O P1. I/O TIM0_OC2 V18 VSS18 ...
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STR750F Figure 4. Required external capacitors when regulators are used SS18 LQFP100 SS18 LFBGA100 18BKP 18 1µ SSBKP V 53 SS18 10 µF V ...
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Pin Description 2.1 Memory map Figure 5. Memory map Addressable Memory Space 4 Gbytes 0xFFFF FFFF APB TO ARM7 BRIDGE 0xFFFF 8000 7 0xE000 0000 0xDFFF FFFF 6 0xC000 0000 0xBFFF FFFF 5 0xA000 0000 0x9FFF FFFF 4 0x9000 0013 ...
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STR750F 3 Electrical parameters 3.1 Parameter conditions Unless otherwise specified, all voltages are referred to V 3.1.1 Minimum and maximum values Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage ...
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Electrical parameters 3.1.4 Loading capacitor The loading conditions used for pin parameter measurement are shown in Figure 6. Pin loading conditions 3.1.5 Pin input voltage The input voltage measurement on a pin of the device is described in Figure 7. ...
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STR750F 3.1.6 Power Supply Schemes When mentioned, some electrical parameters can refer to a dedicated power scheme among the four possibilities. The four different power schemes are described below. Power supply scheme 1: Single external 3.3 V power source Figure ...
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Electrical parameters Power supply scheme 2: Dual external 1.8V and 3.3V supply Figure 9. Power supply scheme 2 V 18_BKP V SS_BKP V DD_IO VREG_DIS 18REG 1.8V V SS18 V DD_IO 3.3V +/-0.3V V SS_IO GP I/Os ...
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STR750F Power supply scheme 3: Single external 5 V power source Figure 10. Power supply scheme 3 V 18_BKP 1µF V SS_BKP VREG_DIS V 18 33nF V SS18 V 18REG 10µF V SS18 V DD_IO 1µF 5.0V +/-0.5V V SS_IO ...
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Electrical parameters Power supply scheme 4: Dual external 1.8 V and 5.0 V supply Figure 11. Power supply scheme 4 V 18_BKP V SS_BKP V DD_IO VREG_DIS 18REG 1.8V V SS18 V DD_IO 5.0V +/-0.5V V SS_IO ...
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STR750F Figure 12. Power consumption measurements in power scheme 1 (regulators enabled) 3.3V Supply I is measured, which corresponds to the total current consumption : DDA_PLL DDA_ADC Figure 13. Power consumption measurements in ...
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Electrical parameters Figure 14. Power consumption measurements in power scheme 3 (regulators enabled) 5.0V Supply I is measured, which corresponds to the total current consumption : DDA_PLL DDA_ADC Figure 15. Power consumption measurements ...
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STR750F 3.2 Absolute maximum ratings Stresses above those listed as “absolute maximum ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device under these conditions is not implied. Exposure to ...
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Electrical parameters 3.2.2 Current characteristics Table 7. Current characteristics Symbol (1) I Total current into V VDD_IO (1) I Total current out of V VSS_IO Output current sunk by any I/O and control pin I IO Output current source by ...
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STR750F 3.3 Operating conditions 3.3.1 General operating conditions Subject to general operating conditions for V Table 9. General operating conditions Symbol Parameter f Internal AHB Clock frequency HCLK f Internal APB Clock frequency PCLK Standard Operating Voltage Power Scheme 1 ...
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Electrical parameters 3.3.3 Embedded voltage regulators Subject to general operating conditions for V Table 11. Embedded voltage regulators Symbol V MVREG power supply MVREG V LPVREG power supply LPVREG Voltage Regulators start-up (1) t time (to reach 90% of final ...
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STR750F 3.3.4 Supply current characteristics The current consumption is measured as described in on page 29. Subject to general operating conditions for V Maximum power consumption For the measurements in conditions: All I/O pins are configured in output push-pull 0 ...
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Electrical parameters Table 13. Maximum power consumption in STOP and STANDBY modes Symbol Parameter LP_PARAM bits: ALL OFF Single supply scheme see LP_PARAM bits: ALL OFF Supply Dual supply scheme see current in LP_PARAM bits: ALL OFF STOP mode Single ...
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STR750F Figure 16. Power consumption in STOP mode in Single supply scheme (3.3 V range) 300 250 TYP (3.3V) MAX (3.6V) 200 150 100 Temp (°C) Figure 18. Power consumption in STANDBY mode (3.3 ...
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Electrical parameters Typical power consumption The following measurement conditions apply to In RUN mode: Program is executed from Flash (except if especially mentioned). The program consists infinite loop. When f A standard 4 MHz crystal source is ...
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STR750F Subject to general operating conditions for V Table 14. Single supply typical power consumption in Run, WFI, Slow and Slow-WFI modes Symbol Para meter Clocked by OSC4M with PLL multiplication, all peripherals enabled in the MRCC_PLCKEN register: f =60 ...
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Electrical parameters Table 15. Dual supply supply typical power consumption in Run, WFI, Slow and Slow-WFI modes To calculate the power consumption in Dual supply mode, refer to the values given in consider that this consumption is split as follows: ...
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STR750F Supply and Clock manager power consumption Table 17. Supply and Clock manager Symbol Parameter Supply current of resonator oscillator I in STOP or WFI mode (LP_PARAM DD(OSC4M) bit: OSC4M ON) FLASH static current consumption in I STOP or WFI ...
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Electrical parameters On-Chip peripheral power consumption Conditions: – DD_IO DDA_ADC – 25° – Clocked by OSC4M with PLL multiplication =32 MHz PCLK . Table 18. On-Chip peripherals Symbol I TIM Timer supply ...
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STR750F 3.3.5 Clock and timing characteristics XT1 external Clock source Subject to general operating conditions for V Table 19. XT1 external Clock source Symbol Parameter External clock source f XT1 frequency XT1 input pin high level V XT1H voltage XT1 ...
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Electrical parameters XRTC1 external Clock source Subject to general operating conditions for V Table 20. XRTC1 external Clock source Symbol Parameter External clock source f XRTC1 frequency XRTC1 input pin high V XRTC1H level voltage XRTC1 input pin low level ...
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STR750F 4/8 MHz Crystal / Ceramic Resonator Oscillator (XT1/XT2) The STR750 system clock or the input of the PLL can be supplied by a OSC4M which MHz clock generated from a 4 MHz or 8 MHz crystal ...
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Electrical parameters OSC32K crystal / ceramic resonator oscillator The STR7 RTC clock can be supplied with a 32.768 kHz Crystal/Ceramic resonator oscillator. All the information given in this paragraph are based on product characterisation with specified typical external components. In ...
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STR750F difference between N+1 consecutive clock rising edges and T difference between N+1 consecutive clock rising edges. N should be kept sufficiently large to have a long term jitter (ex: thousands). For N=1, this becomes the single period jitter. See ...
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Electrical parameters PLL characteristics Subject to general operating conditions for V Table 23. PLL characteristics Symbol PLL input clock f PLL_IN PLL input clock duty cycle f PLL multiplier output clock PLL_OUT f VCO frequency range VCO t PLL lock ...
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STR750F 3.3.6 Memory characteristics Flash memory Subject to general operating conditions for V otherwise specified. Table 25. Flash memory characteristics Symbol Parameter t Word Program PW t Double Word Program PDW t Bank 0 Program (256K) PB0 t Bank 1 ...
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Electrical parameters 3.3.7 EMC characteristics Susceptibilitytests are performed on a sample basis during product characterization. Functional EMS (Electro Magnetic Susceptibility) Based on a simple running application on the product (toggling 2 LEDs through I/O ports), the product is stressed by ...
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STR750F Electro Magnetic Interference (EMI) Based on a simple application running on the product (toggling 2 LEDs through the I/O ports), the product is monitored in terms of emission. This emission test is in line with the norm SAE J ...
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... Static latch-up class DLU Dynamic latch-up class 1. Class description: A Class is an STMicroelectronics internal specification. All its limits are higher than the JEDEC specifications, that means when a device belongs to Class A it exceeds the JEDEC standard. B Class strictly covers all the JEDEC criteria (international standard). ...
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STR750F 3.3.8 I/O port pin characteristics General characteristics Subject to general operating conditions for V Table 31. General characteristics Symbol V Input low level voltage IL V Input high level voltage IH Schmitt trigger voltage V hys hysteresis I Injected ...
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Electrical parameters Figure 25. Connecting unused I/O pins Output driving current The GP I/Os have different drive capabilities: O2 outputs can sink or source up to +/-2 mA outputs can sink or source up to +/-4 mA. G ...
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STR750F Table 32. Output driving current I/O Symbol Type Output low level voltage for a standard (1) V I/O pin when 8 pins are sunk at same OL time O2 Output high level voltage for an I/O pin (2) V ...
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Electrical parameters Output speed Subject to general operating conditions for V Table 33. Output speed I/O Symbol Type F Maximum Frequency max(IO)out Output high to low level fall t f(IO)out O2 time Output low to high level rise t r(IO)out ...
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STR750F NRSTIN and NRSTOUT pins NRSTIN Pin Input Driver is TTL/LVTTL as for all GP I/Os. A permanent pull-up is present which is the same as R NRSTOUT Pin Output Driver is equivalent to the O2 type driver except that ...
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Electrical parameters Figure 27. Recommended NRSTIN pin protection EXTERNAL RESET CIRCUIT 1. The user must ensure that the level on the NRSTIN pin can go below the V NRSTIN and NRSTOUT pins on page 58/71 V DD_IO R PU Filter ...
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STR750F 3.3.9 TB and TIM timer characteristics Subject to general operating conditions for V specified. Refer to Section 3.3.8: I/O port pin characteristics on page 53 input/output alternate function characteristics (output compare, input capture, external clock, PWM output...). Table 35. ...
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Electrical parameters Table 36. PWM Timer (PWM) Symbol Parameter t PWM resolution time res(PWM) Res PWM resolution PWM PWM/DAC output step ( voltage Timer clock period t when internal clock is COUNTER selected Maximum Possible t MAX_COUNT Count ...
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STR750F 3.3.10 Communication interface characteristics Inter IC control interface Subject to general operating conditions for V 2 The ST7 I C interface meets the requirements of the Standard I described in the following table with the ...
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Electrical parameters Figure 28. Typical application with I 4.7kΩ BUS START SDA t t f(SDA) SCL t t h(STA) w(SCKH) 1. Measurement points are done at CMOS levels: 0.3xV 62/ bus and timing diagram V ...
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STR750F 3.3.11 USB characteristics The USB interface is USB-IF certified (Low Speed and High Speed). Table 38. USB characteristics Symbol V Differential Input Sensitivity DI Differential Common Mode V CM Single Ended Receiver Static Output Level Low ...
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Electrical parameters 3.3.12 10-bit ADC characteristics Subject to general operating conditions for V specified. Table 40. 10-bit ADC characteristics Symbol Parameter f ADC clock frequency ADC V Conversion voltage range AIN R External input impedance AIN External capacitor on analog ...
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STR750F ADC Accuracy vs. Negative Injection Current Injecting negative current on specific pins listed in input pin being converted) should be avoided as this significantly reduces the accuracy of the conversion being performed recommended to add a Schottky ...
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Electrical parameters General PCB Design Guidelines To obtain best results, some general design and layout rules should be followed when designing the application PCB to shield the noise-sensitive, analog physical interface from noise-generating CMOS logic signals. Use separate digital and ...
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STR750F Table 42. ADC accuracy ADC Accuracy with f This assumes that the ADC is calibrated Symbol |E | Total unadjusted error Offset error O E Gain Error Differential linearity error ...
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Package characteristics 4 Package characteristics 4.1 Package mechanical data Figure 33. 64-Pin Low Profile Quad Flat Package (10x10) Figure 34. 100-Pin Low Profile Flat Package (14x14) 68/ θ ...
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STR750F Figure 35. 64-Low Profile Fine Pitch Ball Grid Array Package Figure 36. 100-Low Profile Fine Pitch Ball Grid Array Package Figure 37. Recommended PCB design rules (0.80/0.75mm pitch BGA) Dpad Dsm Solder paste – Non solder mask defined pads ...
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Package characteristics 4.2 Thermal characteristics The average chip-junction temperature, T The average chip-junction temperature, T following equation Θ )( Where: – the Ambient Temperature in °C, A – ...
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STR750F 5 Order codes Table 44. Order codes Partnumber STR750FV0T6 STR750FV1T6 STR750FV2T6 (1) STR750FV2H6 STR751FR0T6 STR751FR1T6 STR751FR2T6 (1) STR751FR2H6 STR752FR0T6 STR752FR1T6 STR752FR2T6 (1) STR752FR2H6 STR752FR0T7 STR752FR1T7 STR752FR2T7 (1) STR752FR2H7 STR755FR0T6 STR755FR1T6 STR755FR2T6 (1) STR755FR2H6 STR755FV0T6 STR755FV1T6 STR755FV2T6 (1) STR755FV2H6 1. ...
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Revision history 6 Revision history Table 45. Revision history Date Revision 25-Sep-2006 1 30-Oct-2006 2 72/71 Description of Changes Initial release Added power consumption data for 5V operation in STR750F Section 3 ...
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... STR750F Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. ...