lh79524 NXP Semiconductors, lh79524 Datasheet - Page 44

• Manufacturer Part Number: lh79524
• Description: Lh79524; Lh79525 System-on-chip
• Manufacturer: NXP Semiconductors

LH79524/LH79525
External DMA Handshake Signal Timing
DREQ TIMING
to HIGH again until after nDACK has been asserted.
44
NOTE: * HCLK is an internal signal provided for reference only.
NOTE: tDREQ0L = DREQ0 LOW Pulse Width = 2 HCLK MIN.
Once asserted, DREQ must not transition from LOW
DEOT0/DEOT1
(See Note)
tDREQ1L = DREQ1 LOW Pulse Width = 2 HCLK MIN.
nBLE[1:0]
nDACK1
DACK0/
D[31:0]
A[23:0]
nWEN
HCLK
nCSx
nOE
Figure 24. Read, from Peripheral to Memory, Burst Size = 1
nDACK1
DREQ0,
DREQ1
DACK0
Figure 23. DREQ Timing Restrictions
NXP Semiconductors
Rev. 01 — 16 July 2007
TRANSITON
MUST NOT
DREQ
TRANSITON
DREQ MAY
DACK/DEOT TIMING
DEOT occur in relation to an external bus access to/from
the external peripheral that requested the DMA transfer.
single read or the last word of a burst read from the
requesting peripheral. The remaining diagrams show
timing for data transfers.
These timing diagrams indicate when nDACK and
The first diagram shows the timing with relation to a
ADDRESS
tDREQ0L,
tDREQ1L
DATA
Preliminary data sheet
System-on-Chip
LH79525-5
LH79525-6