lh79524 NXP Semiconductors, lh79524 Datasheet - Page 42

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lh79524

Manufacturer Part Number
lh79524
Description
Lh79524; Lh79525 System-on-chip
Manufacturer
NXP Semiconductors
Datasheet

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LH79524/LH79525
SDRAM MEMORY CONTROLLER WAVEFORMS
SDRAM Burst Read (page already open). Figure 22
shows the waveform and timing for SDRAM to Activate
a Bank and Write.
42
Figure 21 shows the waveform and timing for an
NOTES:
1. SDRAMcmd is the combination of nRAS, nCAS, nSDWE, and nSDCS(X).
2. tOVXXX represents tOVRA, tOVCA, tOVSDW, or tOVSC.
3. tOHXXX represents tOHRA, tOHCA, tOHSDW, or tOHSC.
4. SDCKE is HIGH.
SDRAMcmd
D[31:0]
A[14:0]
DQMx
SCLK
t SDCLK
Figure 21. SDRAM Burst Read
NXP Semiconductors
t OVXXX
Rev. 01 — 16 July 2007
t OVDQ
READ
COLUMN
BANK,
t OHXXX
t OVA
LATENCY = 2
NOP
CAS
tISD tIHD
NOP
DATA n
NOP
t OHDQ
DATA n + 1
READ
DATA n + 2
NOP
DATA n + 3
Preliminary data sheet
NOP
System-on-Chip
LH79525-3

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