lpc3131 NXP Semiconductors, lpc3131 Datasheet - Page 35

• Manufacturer Part Number: lpc3131
• Description: Low-cost, Low-power Arm926ej-s Mcus With High-speed Usb 2.0 Otg, Sd/mmc, And Nand ?ash Controller
• Manufacturer: NXP Semiconductors

NXP Semiconductors
LPC3130_3131_1
Preliminary data sheet
6.29 System control registers
6.30 I2S0/1 interfaces
The System Control Registers (SysCReg) module provides a register interface for some
of the high-level settings in the system such as multiplexers and mode settings. This is an
auxiliary module included in this overview for the sake of completeness.
The I2S0/1 receive and I2S0/1 transmit modules have the following features:
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Audio interface compatible with the I
I2S0/1 receive supports master mode and slave mode.
I2S0/1 transmit supports master mode.
Supports LSB justified words of 16, 18, 20 and 24 bits.
Supports a configurable number of bit clock periods per Word Select period (up to
128 bit clock periods).
Supports DMA transfers.
Transmit FIFO (I
Supports single 16 bit transfers to/from the left or right FIFO.
Supports single 24 bit transfers to/from the left or right FIFO.
Supports 32-bit interleaved transfers, with the lower 16 bits representing the left audio
sample, and the higher 16 bits representing the right audio sample.
Supports two 16-bit audio samples combined in a 32-bit word (2 left or 2 right
samples) to reduce busload.
Provides maskable interrupts for audio status: FIFO underrun/overrun/full/
half_full/not empty for left and right channel separately.
2
S transmit) or receive FIFO (I
Rev. 1 — 9 February 2009
Low-cost, low-power ARM926EJ-S microcontrollers
2
S standard.
2
S receive) of 4 stereo samples.
LPC3130/3131
© NXP B.V. 2009. All rights reserved.
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