lpc3131 NXP Semiconductors, lpc3131 Datasheet
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lpc3131 Summary of contents
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... MHz, 32-bit ARM926EJ D-cache and 16 kB I-cache N Memory Management Unit (MMU) I Internal memory (LPC3130) or 192 kB (LPC3131) embedded SRAM I External memory interface N NAND flash controller with 8-bit ECC N 8/16-bit Multi-Port Memory Controller (MPMC): SDRAM and SRAM I Communication and connectivity N High-speed USB 2 ...
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... Ordering information Type number Package Name Description LPC3130FET180 TFBGA180 plastic thin fine pitch ball grid array package, 180 balls, body 12 LPC3131FET180 TFBGA180 plastic thin fine pitch ball grid array package, 180 balls, body 12 Table 2. Ordering options for LPC3130/3131 Type number Core/bus frequency ...
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... SYSTEM CONTROL CGU IOCONFIG 10-bit ADC EVENT ROUTER RANDOM NUMBER GENERATOR APB slave group 1 TIMER 0/1/2/3 PWM I2C0 I2C1 (1) LPC3131 only Fig 1. LPC3130/3131 block diagram LPC3130_3131_1 Preliminary data sheet Low-cost, low-power ARM926EJ-S microcontrollers JTAG LPC3130/3131 DMA HIGH-SPEED CONTROLLER master master MULTILAYER AHB MATRIX ...
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... NXP Semiconductors 5. Pinning information 5.1 Pinning Fig 2. LPC3130/3131 pinning TFBGA180 package Table 3. Pin allocation table Pin Symbol Pin Symbol Row A 1 EBI_D_10 2 5 mGPIO7 6 9 VDDI 10 13 ADC10B_VDDA33 14 Row B 1 EBI_D_8 2 5 mGPIO8 6 9 PWM_DATA 10 13 ADC10B_GPA2 14 Row C 1 EBI_D_7 2 5 mGPIO9 ...
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... NXP Semiconductors Table 3. Pin allocation table Pin Symbol Pin Symbol Row E 1 EBI_D_3 2 5 VDDE_IOA 6 9 VSSA12 10 13 I2C_SCL1 14 Row F 1 EBI_D_2 2 5 VDDE_IOA 10 13 I2SRX_WS1 14 Row G 1 EBI_NCAS_BLOUT_0 2 5 VDDE_IOA 10 13 SYSCLK_O 14 Row H 1 EBI_DQM_0_NOE 2 5 VDDE_IOA 10 13 GPIO11 14 Row J ...
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... NXP Semiconductors Table 3. Pin allocation table Pin Symbol Pin Symbol Row P 1 USB_VDDA33 2 5 mLCD_DB_7 6 9 mLCD_DB_1 10 13 TRST_N 14 Table 4. Pin description Pin names with prefix m are multiplexed pins. See Pin name BGA Ball Clock Generation Unit FFAST_IN A10 FFAST_OUT ...
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... NXP Semiconductors Table 4. Pin description Pin names with prefix m are multiplexed pins. See Pin name BGA Ball USB_VDDA12_PLL L1 USB_VDDA33_DRV M2 USB_VDDA33 P1 USB_VSSA_TERM L3 USB_GNDA N1 USB_VSSA_REF K4 JTAG JTAGSEL N11 TDI K9 TRST_N P13 TCK M14 TMS P10 SCAN_TDO F10 ARM_TDO E11 BUF_TRST_N F11 BUF_TCK ...
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... NXP Semiconductors Table 4. Pin description Pin names with prefix m are multiplexed pins. See Pin name BGA Ball [3] SPI_MOSI B7 [3] SPI_CS_IN B8 Digital power supply VDDI H3; L7; L12; C12; C6 VSSI A11; C7; D12; G4; L6; L11 Peripheral power supply VDDE_IOA B2; E5; F5; G5; H5 VDDE_IOB L4; ...
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... NXP Semiconductors Table 4. Pin description Pin names with prefix m are multiplexed pins. See Pin name BGA Ball VSSE_IOC B12; D6; D8; D9; G11; L9; L13 LCD Interface [3] mLCD_CSB K8 [3] mLCD_E_RD L8 [3] mLCD_RS P8 [3] mLCD_RW_WR N9 [3] mLCD_DB_0 N8 [3] mLCD_DB_1 P9 [3] mLCD_DB_2 N6 [3] mLCD_DB_3 P6 [3] ...
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... NXP Semiconductors Table 4. Pin description Pin names with prefix m are multiplexed pins. See Pin name BGA Ball 2 I S/Digital Audio Input [3] I2SRX_DATA0 M10 [3] I2SRX_DATA1 G14 [3] I2SRX_BCK0 N10 [3] I2SRX_BCK1 F14 [3] I2SRX_WS0 P11 [3] I2SRX_WS1 F13 2 I S/Digital Audio Output [3] mI2STX_DATA0 M13 [3] mI2STX_BCK0 ...
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... NXP Semiconductors Table 4. Pin description Pin names with prefix m are multiplexed pins. See Pin name BGA Ball External Bus Interface (NAND flash controller) [3] EBI_A_0_ALE B3 [3] EBI_A_1_CLE A2 [3] EBI_D_0 G2 [3] EBI_D_1 F2 [3] EBI_D_2 F1 [3] EBI_D_3 E1 [3] EBI_D_4 E2 [3] EBI_D_5 D1 [3] EBI_D_6 ...
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... NXP Semiconductors Table 5. Supply domains Supply Voltage range Domain SUP1 1.0 V– 1.3 V SUP3 2 3.3 V SUP4 1. 1.95 V (in 1.8 V mode) 2 3.1 V (in 2.8 V mode) SUP5 4.5 V– 5.5 V SUP8 1. 1.95 V (in 1.8 V mode) 2 3.1 V (in 2.8 V mode) [1] When the SDRAM is used, the supply voltage of the NAND flash, SDRAM, and the LCD Interface must be the same, i.e. SUP4 and SUP8 should be connected to the same rail ...
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... NXP Semiconductors 6. Functional description 6.1 ARM926EJ-S The processor embedded in the LPC3130/3131 is the ARM926EJ- member of the ARM9 family of general-purpose microprocessors. The ARM926EJ-S is intended for multi-tasking applications where full memory management, high performance, and low power are important. This module has the following features: • ...
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... APB1 domain APB0 domain reserved 128 kB ISROM reserved 96 kB ISRAM1 96 kB ISRAM0 reserved shadow area 0 GB (1) LPC3131 only. Fig 3. LPC3130/3131 memory map LPC3130_3131_1 Preliminary data sheet Low-cost, low-power ARM926EJ-S microcontrollers 0xFFFF FFFF 0x8000 0000 0x7000 0800 0x7000 0000 APB4 domain ...
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... NXP Semiconductors 6.3 JTAG The Joint Test Action Group (JTAG) interface allows the incorporation of the LPC3130/3131 in a JTAG scan chain. This module has the following features: • ARM926 debug access • Boundary scan 6.4 NAND flash controller The NAND flash controller is used as a dedicated interface to NAND flash devices. ...
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... NXP Semiconductors • Software control mode where the ARM is directly master of the flash device. • Support for 8 bit and 16 bit flash devices. • Support for any page size from 0.5 kB upwards. • Programmable NAND flash timing parameters. • Support for NAND devices. ...
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... NXP Semiconductors – extended wait • One chip select for synchronous memory and two chip selects for static memory devices. • Power-saving modes. • Dynamic memory self-refresh mode supported. • Controller support for and 8 k row address synchronous memory parts. ...
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... This module has the following features: • Capacity (LPC3130) or 192 kB (LPC3131) • On LPC3131 implemented as two independent 96 kB memory banks 6.9 Memory Card Interface (MCI) The MCI controller interface can be used to access memory cards according to the Secure Digital (SD) and Multi-Media Card (MMC) standards. The host controller can be used to interface to small form factor expansion cards compliant to the SDIO card standard as well ...
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... NXP Semiconductors • Supports 1/4-bit SD cards. • Card detection and write protection. • FIFO buffers of 16 bytes deep. • Host pull-up control. • SDIO suspend and resume. • 535 bytes blocks. • Suspend and resume operations. • SDIO Read-wait. • ...
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... NXP Semiconductors – Data is transferred from incrementing memory to a fixed address of a peripheral. The flow is controlled by the peripheral. Peripheral to memory: – Data is transferred from a fixed address of a peripheral to incrementing memory. The flow is controlled by the peripheral. • Supports single data transfers for all transfer types. ...
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... NXP Semiconductors • Level interrupt support. The following blocks can generate interrupts: • NAND flash controller • USB 2.0 high-speed OTG • Event router • 10-bit ADC • UART • LCD • MCI • SPI • I2C0 and I2C1 controllers • Timer0, Timer1, Timer2, and Timer3 • ...
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... NXP Semiconductors ARM DMA 926EJ-S masters 0 1 AHB MULTILAYER MATRIX = master/slave connection supported by matrix (1) LPC3131 only. Fig 5. LPC3130/3131 multi-layer AHB matrix connections This module has the following features: LPC3130_3131_1 Preliminary data sheet Low-cost, low-power ARM926EJ-S microcontrollers USB-OTG AHB MASTER 2 3 asynchronous ...
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... Interrupt Controller – NAND flash controller – MCI SD/SDIO – USB 2.0 high-speed OTG – ISRAM – ISRAM (LPC3131 only) – 128 kB ROM – MPMC 6.14 APB bridge The APB bridge is a bus bridge between the AMBA Advanced High-performance Bus (AHB) and the ARM Peripheral Bus (APB) interface ...
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... NXP Semiconductors Within most clock domains, the output clocks are again grouped into one or more subdomains. All output clocks within one subdomain are either all generated by the same fractional divider or they are connected directly to the base clock. Therefore all output clocks within one subdomain have the same frequency and all output clocks within one clock domain are synchronous because they originate from the same base clock ...
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... NXP Semiconductors • Based on the input of the Watchdog timer (see also generate a system-wide reset in the case of a system stall. clock resources EXTERNAL OSCILLATOR CRYSTAL I2SRX_BCK0 I2SRX_WS0 I2SRX_BCK1 I2SRX_WS1 The LPC3130/3131 has 11 clock domains (n = 11). The number of fractional dividers m depends on the clock domain. ...
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... NXP Semiconductors Fig 7. Block diagram of the Watchdog timer 6.17 Input/Output configuration module (IOCONFIG) The General Purpose Input/Output (GPIO) pins can be controlled through the register interface provided in the IOCONFIG module. Next to several dedicated GPIO pins, most digital I/O pins can also be used as GPIO if they are not required for their normal, dedicated function ...
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... NXP Semiconductors 6.19 Event router The event router extends the interrupt capability of the system by offering a flexible and versatile way of generating interrupts. Combined with the wake-up functionality of the CGU, it also offers a way to wake up the system from suspend mode (with all clocks deactivated). Fig 8. Event router block diagram ...
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... NXP Semiconductors 6.20 Random number generator The Random Number Generator (RNG) generates true random numbers for use in advanced security and Digital Rights Management (DRM) related schemes. These schemes rely upon truly random, i.e. completely unpredictable numbers. This module has the following features: • ...
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... NXP Semiconductors • SIR-IrDA encoder/decoder (from 2400 to 115 kBd). • Supports maskable interrupts. • Supports DMA transfers. 6.23 Pulse Code Modulation (PCM) interface The PCM interface supports the PCM and IOM interfaces. The IOM (ISDN Oriented Modular) interface is primarily used to interconnect telecommunications ICs providing ISDN compatibility. It delivers a symmetrical full-duplex communication link containing user data, control/programming lines, and status channels ...
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... NXP Semiconductors 2 6.25 I C-bus master/slave interface The LPC3130/3131 contains two I This module has the following features: • C-bus interface 0 (I2C0): I2C0 is a standard I open-drain pins. This interface supports functions described in the I specification for speeds up to 400 kHz. This includes multi-master operation and allows powering off this device in a working system while leaving the I functional ...
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... NXP Semiconductors 6.26.1 Pin connections Table 10. Pin descriptions of multiplexed pins Pin Name Default Signal Alternate Video related pin multiplexing mLCD_CSB LCD_CSB mLCD_DB_1 LCD_DB_1 mLCD_DB_0 LCD_DB_0 mLCD_E_RD LCD_E_RD mLCD_RS LCD_RS mLCD_RW_WR LCD_RW_WR mLCD_DB_2 LCD_DB_2 mLCD_DB_3 LCD_DB_3 mLCD_DB_4 LCD_DB_4 mLCD_DB_5 LCD_DB_5 mLCD_DB_6 LCD_DB_6 mLCD_DB_7 ...
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... NXP Semiconductors Table 10. Pin descriptions of multiplexed pins Pin Name Default Signal Alternate mLCD_DB_15 LCD_DB_15 Storage related pin multiplexing mGPIO5 GPIO5 mGPIO6 GPIO6 mGPIO7 GPIO7 mGPIO8 GPIO8 mGPIO9 GPIO9 mGPIO10 GPIO10 NAND related pin multiplexing mNAND_RYBN0 NAND_RYBN0 MCI_DAT_4 mNAND_RYBN1 NAND_RYBN1 MCI_DAT_5 mNAND_RYBN2 NAND_RYBN2 MCI_DAT_6 ...
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... NXP Semiconductors 6.26.2 Multiplexing between LCD and MPMC The multiplexing between the LCD interface and MPMC allows for the following two modes of operation: • MPMC-mode: SDRAM and bus-based LCD or SRAM. • LCD-mode: Dedicated LCD-Interface. The external NAND flash is accessible in both modes. The block diagram involved in the pin interface multiplexing between the EBI, NAND fl ...
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... NXP Semiconductors The EBI unit between the NAND flash interface and the MPMC contains an arbiter that determines which interface is muxed to the outside world. Both NAND flash and SDRAM/SRAM initiate a request to the EBI unit. This request is granted using round-robin arbitration (see 6.26.3 Supply domains As is shown in different supply domain than the LCD interface ...
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... NXP Semiconductors 6.29 System control registers The System Control Registers (SysCReg) module provides a register interface for some of the high-level settings in the system such as multiplexers and mode settings. This is an auxiliary module included in this overview for the sake of completeness. 6.30 I2S0/1 interfaces The I2S0/1 receive and I2S0/1 transmit modules have the following features: • ...
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... NXP Semiconductors 7. Limiting values Table 11. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter All digital I/O pins V input voltage I V output voltage O I output current O Temperature values T junction temperature j T storage temperature stg T ambient temperature amb Electrostatic handling ...
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... NXP Semiconductors 8. Static characteristics Table 12: Static characteristics +85 C unless otherwise specified. amb Symbol Parameter Supply pins V input/output supply DD(IO) voltage V core supply voltage DD(CORE) V oscillator and PLL DD(OSC_PLL) supply voltage V ADC supply voltage DD(ADC) V bus supply voltage BUS V USB analog supply DDA(USB)(3V3) voltage (3 ...
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... NXP Semiconductors Table 12: Static characteristics +85 C unless otherwise specified. amb Symbol Parameter I pull-up current pu I pull-down current pd C input capacitance i Output pins and I/O pins configured as output V output voltage O V HIGH-level output OH voltage V LOW-level output OL voltage I HIGH-level output ...
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... NXP Semiconductors Table 12: Static characteristics +85 C unless otherwise specified. amb Symbol Parameter I HIGH-level OHS short-circuit output current I LOW-level OLS short-circuit output current Z output impedance C0-bus pins I OFF-state output OZ current V HIGH-level input IH voltage V LOW-level input IL voltage V hysteresis voltage ...
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... NXP Semiconductors Table 13. ADC static characteristics +85 C unless otherwise specified; ADC frequency <tbd>. DD(ADC) amb Symbol Parameter V analog input voltage IA C analog input capacitance ia N ADC resolution res(ADC) E differential linearity error D E integral non-linearity L(adj) E offset error ...
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... NXP Semiconductors 1023 1022 1021 1020 1019 1018 7 code out offset error E O (1) Example of an actual transfer curve. (2) The ideal transfer curve. (3) Differential linearity error (E (4) Integral non-linearity (E L(adj) (5) Center of a step of the actual transfer curve. ...
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... NXP Semiconductors Fig 11. Suggested 10-bit ADC interface LPC3130_3131_1 Preliminary data sheet Low-cost, low-power ARM926EJ-S microcontrollers LPC31XX tbd k ADC SAMPLE tbd pF tbd pF V SSA Rev. 1 — 9 February 2009 LPC3130/3131 R vsi AD10B_GPA[0:3] V EXT 002aae136 © NXP B.V. 2009. All rights reserved ...
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... NXP Semiconductors 9. Dynamic characteristics 9.1 LCD controller 9.1.1 Intel 8080 mode Table 14 pF Symbol t su(A) t h(A) t cy(a) t w(en)W t w(en su(D) t h(D) t d(QV) t dis(Q) [1] Timing is determined by the LCD Interface Control Register fields: INVERT_CS = INVERT_E_RD = 0. See LPC3130/3131 user manual . mLCD_RS mLCD_CSB mLCD_RW_WR, mLCD_E_RD ...
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... NXP Semiconductors 9.1.2 Motorola 6800 mode Table 15 pF Symbol t su(A) t h(A) t cy( su(D) t h(D) t d(QV) t dis(Q) t w(en) [1] Timing is derived from the LCD Interface Control Register fields: INVERT_CS = INVERT_E_RD = 0. See LPC3130/3131 user manual . mLCD_CSB mLCD_E_RD mLCD_RS, mLCD_RW_WR mLCD_DB[15:0] (16 bit mode), ...
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... NXP Semiconductors 9.1.3 Serial mode Table 16 pF Symbol Parameter T cy(clk) t w(clk)H t w(clk su(A) t h(A) t su(D) t h(D) t su(S) t h(S) t d(QV) [1] Timing is determined by the LCD Interface Control Register fields SERIAL_CLK_SHIFT = 3; SERIAL_READ_POS = 3. See the LPC3130/3131 user manual . mLCD_CSB mLCD_RS mLCD_DB13 (serial clock) mLCD_DB14 ...
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... NXP Semiconductors 9.2 SRAM controller Table 17. Dynamic characteristics: static external memory interface pF +85 C, unless otherwise specified amb Symbol Parameter Common to read and write cycles t CS LOW to address valid CSLAV time Read cycle parameters t OE LOW to address valid ...
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... NXP Semiconductors EBI_NSTCS_X EBI_A_[15:0] EBI_DQM_0_NOE EBI_NCAS_BLOUT_0 EBI_NRAS_BLOUT_1 EBI_D_[15:0] Fig 15. External memory read access to static memory LPC3130_3131_1 Preliminary data sheet Low-cost, low-power ARM926EJ-S microcontrollers t CSLAV t OELAV t OELOEH t CSLOEL t BLSLAV t BLSLBLSH t CSLBLSL Rev. 1 — 9 February 2009 LPC3130/3131 t CSHOEH t OEHANV t CSHBLSH t BLSHANV t h(DQ) t su(DQ) 002aae161 © ...
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... NXP Semiconductors EBI_NSTCS_X EBI_A_[15:0] EBI_D_[15:0] EBI_NWE EBI_NCAS_BLOUT_0 EBI_NRAS_BLOUT_1 Fig 16. External memory write access to static memory LPC3130_3131_1 Preliminary data sheet Low-cost, low-power ARM926EJ-S microcontrollers t CSLAV t CSLDV t WELWEH t CSLWEL t WELDV t BLSLBLSH t CSLBLSL Rev. 1 — 9 February 2009 LPC3130/3131 t BLSHANV t WEHANV t WEHDNV t BLSHDNV 002aae162 © NXP B.V. 2009. All rights reserved. ...
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... NXP Semiconductors 9.3 SDRAM controller Table 18. Dynamic characteristics of SDR SDRAM memory interface +85 C, unless otherwise specified; V amb Symbol Parameter f operating frequency oper T clock cycle time CLCL t clock LOW time CLCX t clock HIGH time CHCX t output delay time d(o) t output hold time ...
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... NXP Semiconductors T t CHCX EBI_CLKOUT EBI_NRAS_BLOUT EBI_NCAS_BLOUT EBI_NWE EBI_CKE EBI_NDYCS EBI_DQMx EBI_A_[15:2] EBI_D_[15:0] EBI_CKE is HIGH. Fig 17. SDRAM burst read timing LPC3130_3131_1 Preliminary data sheet Low-cost, low-power ARM926EJ-S microcontrollers CLCL t CLCX t t d(o) h(o) READ NOP t d(o) t h(A) BANK, t su(D) COLUMN CAS LATENCY = 2 Rev. 1 — 9 February 2009 ...
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T CLCL t CHCX EBI_CLKOUT EBI_CKE EBI_NRAS_BLOUT EBI_NCAS_BLOUT EBI_NWE EBI_CKE EBI_NDYCS EBI_DQMx EBI_A_[15:2] EBI_D_[15:0] Fig 18. SDRAM bank activate and write timing t CLCX t d( d(o) h(o) ACTIVE t h(A) BANK, ROW t d(AV) t h(o) WRITE ...
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... NXP Semiconductors 9.4 NAND flash memory controller Table 19 +85 C, unless otherwise specified. amb Symbol t REH CLS t CLH t ALS t ALH [1] T HCLK [2] See registers NandTiming1 and NandTiming2 in the LPC3130/3131 user manual . Fig 19. LPC3130_3131_1 Preliminary data sheet Low-cost, low-power ARM926EJ-S microcontrollers Dynamic characteristics of the NAND fl ...
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... NXP Semiconductors 9.5 Crystal oscillator Table 20: Dynamic characteristics: crystal oscillator Symbol Parameter f oscillator frequency osc clock duty cycle clk C crystal capacitance xtal t start-up time startup P drive power drive 9.6 SPI Table 21 +85 C for industrial applications amb Symbol SPI master T SPICYC t SPICLKH ...
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... NXP Semiconductors Fig 20. Fig 21. LPC3130_3131_1 Preliminary data sheet Low-cost, low-power ARM926EJ-S microcontrollers T SPICYC SCK (CPOL = 0) SCK (CPOL = 1) t SPIQV DATA VALID MOSI MISO DATA VALID SPI master timing (CPHA = 1) SCK (CPOL = 0) SCK (CPOL = 1) t SPIQV DATA VALID MOSI DATA VALID MISO SPI master timing (CPHA = 0) Rev. 1 — ...
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... NXP Semiconductors Fig 22. Fig 23. LPC3130_3131_1 Preliminary data sheet Low-cost, low-power ARM926EJ-S microcontrollers T SPICYC SCK (CPOL = 0) SCK (CPOL = 1) MOSI DATA VALID t SPIQV MISO DATA VALID SPI slave timing (CPHA = 1) SCK (CPOL = 0) SCK (CPOL = 1) MOSI DATA VALID t SPIQV MISO DATA VALID SPI slave timing (CPHA = 0) Rev. 1 — ...
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... NXP Semiconductors 9.6.1 Texas Instruments synchronous serial mode (SSI mode) Table 22. Dynamic characteristic: SPI interface (SSI mode + (SUP3) over specified ranges. amb DD(IO) Symbol Parameter t SPI_MISO set-up time su(SPI_MISO) [1] Parameters are valid over operating temperature range unless otherwise specified. ...
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... NXP Semiconductors 2 9.7 I S-bus interface Table 23. Dynamic characteristics +85 C for industrial applications amb Symbol Parameter common to input and output T clock cycle time cy(clk) t rise time r t fall time f output t pulse width HIGH WH t pulse width LOW WL t data output valid time ...
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... NXP Semiconductors I2SRX_BCK0 or I2SRX_BCK1 I2SRX_DATA0 or I2SRX_DATA1 I2SRX_WS0 or I2SRX_WS1 Fig 26 9.8 I C-bus interface Table 24. Dynamic characteristics +85 C. amb Symbol Parameter f SCL clock frequency SCL t output fall time f(o) t rise time r t fall time f t bus free time between a STOP and ...
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... NXP Semiconductors SDA t BUF SCL HD;STA Remark: Signals SDA and SCL correspond to pins I2C_SDAx and I2C_SCLx ( 1). 2 Fig 27. I C-bus pins clock timing 9.9 USB interface Table 25. Dynamic characteristics: USB pins (high-speed pF 1 Symbol Parameter t rise time ...
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... NXP Semiconductors T PERIOD differential data lines Fig 28. Differential data-to-EOP transition skew and EOP width 9.10 10-bit ADC Table 26: Dynamic characteristics: 10-bit ADC Symbol Parameter f sampling frequency s t conversion time conv LPC3130_3131_1 Preliminary data sheet Low-cost, low-power ARM926EJ-S microcontrollers crossover point crossover point ...
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Application information Table 27. LCD panel connections TFBGA pin # Pin name K8 mLCD_CSB/EBI_nSTCS0 L8 mLCD_E_RD/EBI_CKE P8 mLCD_RS/EBI_NDYCS N9 mLCD_RW_WR/EBI_DQM1 N8 mLCD_DB0/EBI_CLKOUT P9 mLCD_DB1/EBI_NSTCS1 N6 mLCD_DB2/EBI_A2 P6 mLCD_DB3/EBI_A3 N7 mLCD_DB3/EBI_A4 P7 mLCD_DB5/EBI_A5 K6 mLCD_DB6/EBI_A6 P5 mLCD_DB3/EBI_A7 N5 mLCD_DB3/EBI_A8 L5 ...
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... NXP Semiconductors 11. Marking Table 28. Line A LPC3130_3131_1 Preliminary data sheet Low-cost, low-power ARM926EJ-S microcontrollers LPC3130/3131 Marking Marking Description LPC3130/3131 BASIC_TYPE Rev. 1 — 9 February 2009 LPC3130/3131 © NXP B.V. 2009. All rights reserved ...
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... NXP Semiconductors 12. Package outline TFBGA180: thin fine-pitch ball grid array package; 180 balls ball A1 index area ball index area DIMENSIONS (mm are the original dimensions) UNIT max 1.20 0.40 0.80 mm nom 1.06 0.35 0.71 min 0.95 0.30 0.65 OUTLINE VERSION ...
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... NXP Semiconductors 13. Abbreviations Table 29. Acronym A/D ADC AHB AMBA APB ATA BIU CE CGU CRC DFU DMA DRM DSP EBI ECC EOP ESD FIFO FPGA GF INTC IOCONFIG IOM IrDA IROM ISRAM ISROM JTAG LSB MCI MCU MMC MPMC OTG PCM PHY PLL PWM ...
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... NXP Semiconductors Table 29. Acronym RNG ROM SD SDHC SDIO SDR SE0 SIR SPI SSI SysCReg TAP TDO UART USB UTMI WDT LPC3130_3131_1 Preliminary data sheet Low-cost, low-power ARM926EJ-S microcontrollers Abbreviations …continued Description Random Number Generator Read-Only Memory Secure Digital Secure Digital High Capacity ...
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... NXP Semiconductors 14. Revision history Table 30: Revision history Document ID Release date LPC3130_3131_1 20090209 LPC3130_3131_1 Preliminary data sheet Low-cost, low-power ARM926EJ-S microcontrollers Data sheet status Change notice Preliminary data sheet - Rev. 1 — 9 February 2009 LPC3130/3131 Supersedes - © NXP B.V. 2009. All rights reserved ...
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... Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice ...
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... NXP Semiconductors 17. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2.1 Key features . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 4 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 5 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 6 Functional description . . . . . . . . . . . . . . . . . . 13 6.1 ARM926EJ 6.2 Memory map 6.3 JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 6.4 NAND flash controller . . . . . . . . . . . . . . . . . . . 15 6.5 Multi-Port Memory Controller (MPMC 6.6 External Bus Interface (EBI 6.7 Internal ROM Memory . . . . . . . . . . . . . . . . . . 17 6.8 Internal RAM memory ...