lpc2888fet180 NXP Semiconductors, lpc2888fet180 Datasheet - Page 23

• Manufacturer Part Number: lpc2888fet180
• Description: 16/32-bit Arm Microcontrollers; 8 Kb Cache, Up To 1 Mb Flash, Hi-speed Usb 2.0 Device, And Sdram Memory Interface
• Manufacturer: NXP Semiconductors

NXP Semiconductors
LPC2880_LPC2888_2
Preliminary data sheet
6.20.1 Features
6.20.2 Reset
6.20.3 Crystal oscillator
6.20.4 PLLs
6.20 Clocking and power control
Clocking in the LPC2880/2888 is controlled by a versatile CGU, so that system and
peripheral requirements may be met while allowing optimization of power consumption.
Clocks to most functions may be turned off if not needed, and may be enabled and
disabled by selected events through the Event Router.
Clock sources include a high frequency (1 MHz to 20 MHz) crystal oscillator and a 32 kHz
RTC oscillator. Higher frequency clocks may be generated through the use of two
programmable PLLs.
Reset of individual functional blocks is also controlled by the CGU. Full chip reset can be
initiated by the external reset pin or by the watchdog timer.
The LPC2880/2888 has two sources of reset: the RESET pin and the watchdog reset. The
RESET pin includes an on-chip pull-up. RESET must remain low at power-up for 1 ms
after power supply voltages are stable. This includes on-chip DC-to-DC converter
voltages.
When either reset is removed, the processor begins executing at address 0, which is the
Reset vector. At that point, all of the processor and peripheral registers have been
initialized to predetermined values.
The on-chip watchdog timer can cause a chip reset if not updated within a programmable
time interval. A status register allows software to determine if a reset was caused by the
watchdog timer. The watchdog timer can also be configured to generate an interrupt if
desired.
Software reset of many individual functional blocks may be performed via registers within
the CGU.
The main oscillator is the basis for the clocks most chip functions use by default. The
oscillator may be used with crystal frequencies from 1 MHz to 20 MHz.
The LPC2880/2888 includes two PLLs: the main PLL provides clocks to most chip
functions, and a high-speed PLL that can be used to generate faster clocks for selected
chip functions. Each PLL can be driven from several clock sources. These include the
main oscillator (1 MHz to 20 MHz), the RTC oscillator (32 kHz), the bit clock or word select
inputs of the I
output clock from the other PLL.
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•
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Power and performance control provided by versatile clock generation to individual
functional blocks.
Multiple clock sources including external crystal and programmable PLLs.
Individual control of software reset to many functional blocks.
2
S input channel, the clock input from the SD/MMC card interface, or the
Rev. 02 — 21 November 2006
16/32-bit ARM microcontrollers with external memory interface
LPC2880; LPC2888
© NXP B.V. 2006. All rights reserved.
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