p87c591vfb NXP Semiconductors, p87c591vfb Datasheet - Page 128
p87c591vfb
Manufacturer Part Number
p87c591vfb
Description
Single-chip 8-bit Microcontroller With Can Controller
Manufacturer
NXP Semiconductors
Datasheet
1.P87C591VFB.pdf
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Philips Semiconductors
20.3.1
Table 88 ADC Control Register (address C5H); Reset value = xx00 0000B
Table 89 Description of ADCON bits
Table 90 ADC status
Table 91 Selected analog channel
2000 Jul 26
Single-chip 8-bit microcontroller with CAN controller
ADC.1
2 to 0
BIT
AADR2
7
7
6
5
4
3
ADCI
ADC C
0
0
1
1
0
0
0
0
1
1
ONTROL
AADR2 to
SYMBOL
AADR0
ADC.1
ADC.0
ADC.0
ADCS
ADCI
6
R
AADR1
EGISTER
ADCS
0
1
0
1
0
0
1
1
0
0
Bit 1 of ADC result.
Bit 0 of ADC result.
Reserved for future use.
ADC interrupt flag. This flag is set when an A/D conversion result is ready to be read.
An interrupt is invoked if its is enabled. The flag may be cleared by the interrupt service
routine. While this flag is set, the ADC cannot start a new conversion. ADCI cannot be
set by software.
ADC start and status. Setting this bit starts an A/D conversion. It is set by software.
The ADC logic ensures that this signal is HIGH while the ADC is busy. On completion of
the conversion. ADCS is reset immediately after the interrupt flag has been set. ADCS
cannot be reset by software. A new conversion may not be started while either ADCS or
ADCI is high (see Table 90).
If ADDCI is cleared by software while ADCS is set at the same time, a new A/D
conversion with the same channel number may be started.
But it is recommended to reset ADCI before ADCS is set.
Analogue input select: This binary coded address selects one of the six analogue port
bits of P1 to be input to the converter. It can only be changed when ADCI and ADCS are
both LOW.
ADEX
(ADCON)
5
ADC not busy; a conversion can be started
ADC busy; start of a new conversion is blocked
Conversion completed; start of a new conversion requires ADCI=0
Conversion completed; start of a new conversion requires ADCI=0
AADR0
0
1
0
1
0
1
ADCI
4
128
ADCS
3
DESCRIPTION
SELECTED ANALOG CHANNEL
ADC STATUS
AADR2
2
ADC0 (P1.2)
ADC1 (P1.3)
ADC2 (P1.4)
ADC3 (P1.5)
ADC4 (P1.6)
ADC5 (P1.7)
AADR1
Preliminary Specification
1
P8xC591
AADR0
0
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