p87lpc778 NXP Semiconductors, p87lpc778 Datasheet - Page 55

• Manufacturer Part Number: p87lpc778
• Description: Cmos Single-chip 8-bit 80c51 Microcontroller 128-byte Data Ram, 8 Kb Otp
• Manufacturer: NXP Semiconductors

Philips Semiconductors
9397 750 12378
Product data
8.15.9 More about UART Mode 1
RECEIVE enable SHIFT CLOCK to the alternate output function line of P3.1. SHIFT
CLOCK makes transitions at S3P1 and S6P1 of every machine cycle. At S6P2 of
every machine cycle in which RECEIVE is active, the contents of the receive shift
register are shifted to the left one position. The value that comes in from the right is
the value that was sampled at the P3.0 pin at S5P2 of the same machine cycle.
As data bits come in from the right, ‘1’s shift out to the left. When the ‘0’ that was
initially loaded into the rightmost position arrives at the leftmost position in the shift
register, it flags the RX Control block to do one last shift and load SBUF. At S1P1 of
the 10th machine cycle after the write to SCON that cleared RI, RECEIVE is cleared
as RI is set.
Ten bits are transmitted (through TxD), or received (through RxD): a start bit (0),
8 data bits (LSB first), and a stop bit (1). On receive, the stop bit goes into RB8 in
SCON. In the P87LPC778 the baud rate is determined by the Timer1 overflow rate.
Figure 24
associated timings for transmit receive.
Transmission is initiated by any instruction that uses SBUF as a destination register.
The ‘write to SBUF’ signal also loads a ‘1’ into the 9th bit position of the transmit shift
register and flags the TX Control unit that a transmission is requested. Transmission
actually commences at S1P1 of the machine cycle following the next rollover in the
divide-by-16 counter. (Thus, the bit times are synchronized to the divide-by-16
counter, not to the ‘write to SBUF’ signal.)
The transmission begins with activation of SEND which puts the start bit at TxD. One
bit time later, DATA is activated, which enables the output bit of the transmit shift
register to TxD. The first shift pulse occurs one bit time after that.
As data bits shift out to the right, zeros are clocked in from the left. When the MSB of
the data byte is at the output position of the shift register, then the ‘1’ that was initially
loaded into the 9th position is just to the left of the MSB, and all positions to the left of
that contain zeros. This condition flags the TX Control unit to do one last shift and
then deactivate SEND and set TI. This occurs at the 10th divide-by-16 rollover after
‘write to SBUF.’
Reception is initiated by a detected 1-to-0 transition at RxD. For this purpose RxD is
sampled at a rate of 16 times whatever baud rate has been established. When a
transition is detected, the divide-by-16 counter is immediately reset, and 1FFH is
written into the input shift register. Resetting the divide-by-16 counter aligns its
rollovers with the boundaries of the incoming bit times.
The 16 states of the counter divide each bit time into 16ths. At the 7th, 8th, and 9th
counter states of each bit time, the bit detector samples the value of RxD. The value
accepted is the value that was seen in at least 2 of the 3 samples. This is done for
noise rejection. If the value accepted during the first bit time is not ‘0’, the receive
circuits are reset and the unit goes back to looking for another 1-to-0 transition. This
is to provide rejection of false start bits. If the start bit proves valid, it is shifted into the
input shift register, and reception of the rest of the frame will proceed.
shows a simplified functional diagram of the serial port in Mode 1, and
Rev. 01 — 31 March 2004
CMOS single-chip 8-bit microcontroller
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
P87LPC778
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