p87lpc778 NXP Semiconductors, p87lpc778 Datasheet - Page 24

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p87lpc778

Manufacturer Part Number
p87lpc778
Description
Cmos Single-chip 8-bit 80c51 Microcontroller 128-byte Data Ram, 8 Kb Otp
Manufacturer
NXP Semiconductors
Datasheet

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Product data
If PWMCON1 is written with Transfer set without Run being enabled the transfer will
never take place.
If a subsequent write sets Run without Transfer the compare and counter values will
not be updated.
If Transfer and Run are set, and prior to underflow there is a subsequent load of
PWMCON0 which sets Run but not Transfer, the transfer will never take place. The
compare and counter values that existed prior to the update attempt will be used.
As outlined above the Transfer bit can be polled to determine when the transfer
occurs. Unless there is a compelling reason to do otherwise, it is recommended that
both Run, PWMCON0.7, and Transfer, PWMCON0.6, be set when PWMCON0 is
written. When the Run bit, PWMCON0.7, is cleared the PWM outputs take on the
state they had just prior to the bit being cleared. In general this state is not known.
In order to place the outputs in a known state when Run is cleared the Compare
registers can be written to either the ‘always 1’ or ‘always 0’ so the output will have
the output desired when the counter is halted. After this PWMCON0 should be written
with the Transfer and Run bits are enabled. After this is done PWMCON0 is polled to
find that the Transfer has taken place. Once the transfer has occurred the Run bit in
PWMCON0 can be cleared. The outputs will retain the state they had just prior to the
Run being cleared.
Table 18:
Reset value: 00H
Table 19:
Bit
7
6
5
4
Bit
Symbol
Symbol
RUN
XFER
PWM3I
PWM2I
PWMCON0 - PWM control register 0 (address 0DAH) bit allocation
PWMCON0 - PWM control register 0 (address 0DAH) bit description
RUN
7
Rev. 01 — 31 March 2004
Value
0
1
0
1
0
1
0
1
XFER
6
PWM3I
Description
Counter halted and preset value loaded. If Brake is
asserted, PWMx output will be equal to the value of the
corresponding PWMxB bit (PWMCON1[3:0]). If Brake is
not asserted, PWMx output will be equal to the Value after
compare.
Counter run
Counter run
Counter and compare shadow registers are not
connected to the active registers
PWM3 output is non-inverted. Output is a ‘1’ from the start
of the cycle until compare; ‘0’ thereafter.
PWM3 output is inverted. Output is a ‘0’ from the start of
the cycle until compare; ‘0’ thereafter.
PWM2 output is non-inverted. Output is a ‘1’ from the start
of the cycle until compare; ‘0’ thereafter.
PWM2 output is inverted. Output is ‘0’ from the start of the
cycle until compare; ‘1’ thereafter.
5
PWM2I
4
CMOS single-chip 8-bit microcontroller
3
-
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
PWM1I
P87LPC778
2
PWM0I
1
24 of 79
0
-

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