p89lpc9351 NXP Semiconductors, p89lpc9351 Datasheet - Page 23

• Manufacturer Part Number: p89lpc9351
• Description: 8-bit Microcontroller With Accelerated Two-clock 80c51 Core 8 Kb 3 V Byte-erasable ?ash With 8-bit Adc
• Manufacturer: NXP Semiconductors

NXP Semiconductors
P89LPC9351_1
Preliminary data sheet
7.5 Clock output
7.6 On-chip RC oscillator option
7.7 Watchdog oscillator option
7.8 External clock input option
7.9 Clock sources switch on the fly
The P89LPC9351 supports a user-selectable clock output function on the
XTAL2/CLKOUT pin when crystal oscillator is not being used. This condition occurs if
another clock source has been selected (on-chip RC oscillator, watchdog oscillator,
external clock input on XTAL1) and if the RTC and WDT are not using the crystal oscillator
as their clock source. This allows external devices to synchronize to the P89LPC9351.
This output is enabled by the ENCLK bit in the TRIM register.
The frequency of this clock output is
in Idle mode, it may be turned off prior to entering Idle, saving additional power.
The P89LPC9351 has a 6-bit TRIM register that can be used to tune the frequency of the
RC oscillator. During reset, the TRIM value is initialized to a factory preprogrammed value
to adjust the oscillator frequency to 7.373 MHz
applications can write to the TRIM register to adjust the on-chip RC oscillator to other
frequencies. When the clock doubler option is enabled (UCFG2.7 = 1), the output
frequency is 14.746 MHz. If CCLK is 8 MHz or slower, the CLKLP SFR bit (AUXR1.7) can
be set to logic 1 to reduce power consumption. On reset, CLKLP is logic 0 allowing
highest performance access. This bit can then be set in software if CCLK is running at
8 MHz or slower. When clock doubler option is enabled, BOE1 bit (UCFG1.5) and BOE0
bit (UCFG1.3) are required to hold the device in reset at power-up until V
its specified level.
The watchdog has a separate oscillator which has a frequency of 400 kHz, calibrated to
frequency is not needed.
In this configuration, the processor clock is derived from an external source driving the
P3.1/XTAL1 pin. The rate may be from 0 Hz up to 18 MHz. The P3.0/XTAL2 pin may be
used as a standard port pin or a clock output. When using an oscillator frequency above
12 MHz, BOE1 bit (UCFG1.5) and BOE0 bit (UCFG1.3) are required to hold the device in
reset at power-up until V
P89LPC9351 can implement clock source switch in any sources of watchdog oscillator,
7 MHz/14 MHz IRC oscillator, external clock source (external crystal or external clock
input) during code is running. CLKOK bit in CLKCON register is used to indicate the clock
switch status. CLKOK is cleared when starting clock source switch and set when
completed. Notice that when CLKOK is ‘0’, writing to CLKCON register is not allowed.
5 % at room temperature. This oscillator can be used to save power when a high clock
Rev. 01 — 19 November 2008
DD
has reached its specified level.
1
2
that of the CCLK. If the clock output is not needed
1 % at room temperature. End-user
8-bit microcontroller with 8-bit ADC
P89LPC9351
© NXP B.V. 2008. All rights reserved.
DD
has reached
23 of 74