p89lpc9351 NXP Semiconductors, p89lpc9351 Datasheet
p89lpc9351
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p89lpc9351 Summary of contents
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... The P89LPC9351 is a single-chip microcontroller, available in low cost packages, based on a high performance processor architecture that executes instructions in two to four clocks, six times the rate of standard 80C51 devices. Many system-level functions have been incorporated into the P89LPC9351 in order to reduce component count, board space, and system cost. 2. Features 2 ...
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... I Controlled slew rate port outputs to reduce EMI. Outputs have approximately 10 ns minimum ramp times. I Only power and ground connections are required to operate the P89LPC9351 when internal reset option is selected. I Four interrupt priority levels. I Eight keypad interrupt inputs, plus two additional external interrupt inputs ...
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... NXP Semiconductors 3. Ordering information Table 1. Type number P89LPC9351FA P89LPC9351FDH 3.1 Ordering options Table 2. Type number P89LPC9351FA P89LPC9351FDH P89LPC9351_1 Preliminary data sheet Ordering information Package Name Description PLCC28 plastic leaded chip carrier; 28 leads TSSOP28 plastic thin shrink small outline package; 28 leads; body width 4.4 mm ...
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... KEYPAD INTERRUPT WATCHDOG TIMER AND OSCILLATOR PROGRAMMABLE CPU OSCILLATOR DIVIDER clock ON-CHIP RC CONFIGURABLE OSCILLATOR OSCILLATOR WITH CLOCK DOUBLER Rev. 01 — 19 November 2008 P89LPC9351 8-bit microcontroller with 8-bit ADC TXD UART RXD SCL 2 I C-BUS SDA SPICLK MOSI SPI MISO SS REAL-TIME CLOCK/ ...
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... Preliminary data sheet CMP2 CIN2B CIN2A CIN1B PORT 0 CIN1A CMPREF CMP1 T1 P89LPC9351 XTAL2 PORT 3 XTAL1 002aad556 Rev. 01 — 19 November 2008 P89LPC9351 8-bit microcontroller with 8-bit ADC SS TXD RXD SCL T0 SDA INT0 PORT 1 INT1 RST OCB AD00 OCC ICB AD03 AD02 OCD ...
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... P1.2/T0/SCL 13 P2.2/MOSI P2.3/MISO 14 P89LPC9351 TSSOP28 pin configuration 5 P1.6/OCB P1.5/RST P3.1/XTAL1 8 P89LPC9351FA 9 P3.0/XTAL2/CLKOUT P1.4/INT1 10 P1.3/INT0/SDA 11 P89LPC9351 PLCC28 pin configuration Rev. 01 — 19 November 2008 P89LPC9351 8-bit microcontroller with 8-bit ADC 28 P2.7/ICA 27 P2.6/OCA 26 P0.1/CIN2B/KBI1/AD10 25 P0.2/CIN2A/KBI2/AD11 24 P0.3/CIN1B/KBI3/AD12 23 P0.4/CIN1A/KBI4/DAC1/AD13 22 P0.5/CMPREF/KBI5 ...
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... AD13 — ADC1 channel 3 analog input. I/O P0.5 — Port 0 bit 5. High current source. I CMPREF — Comparator reference (negative) input. I KBI5 — Keyboard input 5. Rev. 01 — 19 November 2008 P89LPC9351 8-bit microcontroller with 8-bit ADC and Table 10 “Static characteristics” © NXP B.V. 2008. All rights reserved. for ...
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... OCB — Output Compare B I/O P1.7 — Port 1 bit 7. High current source. O OCC — Output Compare C. I AD00 — ADC0 channel 0 analog input. Rev. 01 — 19 November 2008 P89LPC9351 8-bit microcontroller with 8-bit ADC and Table 10 “Static characteristics” © NXP B.V. 2008. All rights reserved. for ...
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... Each port pin is configured independently. Refer to Section 7.16.1 “Port configurations” details. All pins have Schmitt trigger inputs. Port 3 also provides various special functions as described below: Rev. 01 — 19 November 2008 P89LPC9351 8-bit microcontroller with 8-bit ADC and Table 10 “Static characteristics” and Table 10 “Static characteristics” ...
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... RTC/system timer. I Ground reference. I Power supply: This is the power supply voltage for normal operation as well as Idle and Power-down modes. Rev. 01 — 19 November 2008 P89LPC9351 8-bit microcontroller with 8-bit ADC © NXP B.V. 2008. All rights reserved ...
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... NXP Semiconductors 7. Functional description Remark: Please refer to the P89LPC9351 User manual for a more detailed functional description. 7.1 Special function registers Remark: SFR accesses are restricted in the following ways: • User must not attempt to access any SFR locations not defined. • Accesses to any defined SFR locations must be strictly for the functions for the SFRs. ...
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Table 4. Special function registers * indicates SFRs that are bit addressable. Name Description SFR Bit functions and addresses addr. MSB Bit address E7 ACC* Accumulator E0H ADCON0 A/D control 8EH ENBI0 register 0 ADCON1 A/D control 97H ENBI1 register ...
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Table 4. Special function registers …continued * indicates SFRs that are bit addressable. Name Description SFR Bit functions and addresses addr. MSB AD1DAT1 A/D_1 data D6H register 1 AD1DAT2 A/D_1 data D7H register 2 AD1DAT3 A/D_1 data F5H register 3 ...
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Table 4. Special function registers …continued * indicates SFRs that are bit addressable. Name Description SFR Bit functions and addresses addr. MSB CMP2 Comparator 2 ADH - control register DEECON Data EEPROM F1H EEIF control register DEEDAT Data EEPROM F2H ...
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Table 4. Special function registers …continued * indicates SFRs that are bit addressable. Name Description SFR Bit functions and addresses addr. MSB 2 I2DAT I C-bus data DAH register I2SCLH Serial clock DDH generator/SCL duty cycle register high I2SCLL Serial ...
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Table 4. Special function registers …continued * indicates SFRs that are bit addressable. Name Description SFR Bit functions and addresses addr. MSB IP1H Interrupt F7H PAEEH priority 1 high KBCON Keypad control 94H - register KBMASK Keypad 86H interrupt mask ...
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Table 4. Special function registers …continued * indicates SFRs that are bit addressable. Name Description SFR Bit functions and addresses addr. MSB Bit address 87 P0* Port 0 80H T1/KB7 Bit address 97 P1* Port 1 90H OCC Bit address ...
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Table 4. Special function registers …continued * indicates SFRs that are bit addressable. Name Description SFR Bit functions and addresses addr. MSB PT0AD Port 0 digital F6H - input disable RSTSRC Reset source DFH - register RTCCON RTC control D1H ...
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Table 4. Special function registers …continued * indicates SFRs that are bit addressable. Name Description SFR Bit functions and addresses addr. MSB Bit address 8F TCON* Timer 0 and 1 88H TF1 control TCR20* CCU control C8H PLEEN register 0 ...
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... BRGR1 and BRGR0 must only be written if BRGEN in BRGCON SFR is logic 0. If any are written while BRGEN = 1, the result is unpredictable. [3] The RSTSRC register reflects the cause of the P89LPC9351 reset except BOIF bit. Upon a power-up reset, all reset source flags are cleared except POF and BOF; the power-on reset value is x011 0000. ...
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Table 5. Extended special function registers Name Description SFR Bit functions and addresses addr. BODCFG BOD FFC8H configuration register CLKCON CLOCK Control FFDEH CLKOK register PGACON0 PGA0 control FFCAH ENPGA0 register PGACON1 PGA1 control FFE1H ENPGA1 register PGACON0B PGA0 control ...
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... NXP Semiconductors 7.2 Enhanced CPU The P89LPC9351 uses an enhanced 80C51 CPU which runs at six times the speed of standard 80C51 devices. A machine cycle consists of two CPU clock cycles, and most instructions execute in one or two machine cycles. 7.3 Clocks 7.3.1 Clock definitions The P89LPC9351 device has several internal clocks as defined below: OSCCLK — ...
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... Idle mode, it may be turned off prior to entering Idle, saving additional power. 7.6 On-chip RC oscillator option The P89LPC9351 has a 6-bit TRIM register that can be used to tune the frequency of the RC oscillator. During reset, the TRIM value is initialized to a factory preprogrammed value to adjust the oscillator frequency to 7.373 MHz applications can write to the TRIM register to adjust the on-chip RC oscillator to other frequencies ...
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... Low power select The P89LPC9351 is designed to run at 18 MHz (CCLK) maximum. However, if CCLK is 8 MHz or slower, the CLKLP SFR bit (AUXR1.7) can be set to logic 1 to lower the power consumption further. On any reset, CLKLP is logic 0 allowing highest performance access ...
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... CODE Code memory space, accessed as part of program execution and via the MOVC instruction. The P89LPC9351 has on-chip Code memory. The P89LPC9351 also has 512 bytes of on-chip data EEPROM that is accessed via SFRs (see Section 7.14 Data RAM arrangement The 768 bytes of on-chip RAM are organized as shown in Table 6 ...
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... LOW in the next cycle, the interrupt request flag IEn in TCON is set, causing an interrupt request external interrupt is enabled when the P89LPC9351 is put into Power-down or Idle mode, the interrupt will cause the processor to wake-up and resume operation. Refer to Section 7.18 “Power reduction modes” ...
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... RTCF ERTC (RTCCON.1) WDOVF any CCU interrupt EEIF ENADCI0 ADCI0 ENADCI1 ADCI1 ENBI0 BNDI0 ENBI1 BNDI1 EADEE (P89LPC9351) Fig 6. Interrupt sources, interrupt enables, and power-down wake-up sources P89LPC9351_1 Preliminary data sheet IE0 EX0 IE1 EX1 BOIF EBO KBIF EKBI EWDRT CMF2 ...
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... NXP Semiconductors 7.16 I/O ports The P89LPC9351 has four I/O ports: Port 0, Port 1, Port 2 and Port 3. Ports 0, 1, and 2 are 8-bit ports, and Port 2-bit port. The exact number of I/O pins available depends upon the clock and reset options chosen, as shown in Table 7. Clock source ...
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... Pin P1.5 is input only. Pins P1.2 and P1.3 are configurable for either input-only or open-drain. Every output on the P89LPC9351 has been designed to sink typical LED drive current. However, there is a maximum total output current for all ports which must not be exceeded. Please refer to All ports pins that can function as an output have slew rate controlled outputs to limit noise generated by quickly switching output signals ...
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... BOD reset voltage should be lower than BOD interrupt trip point. BOD EEPROM/FLASH is used for flash/Data EEPROM programming/erase protection and has only 1 trip voltage of 2.4 V. Please refer to P89LPC9351 User manual for detail configurations. If brownout detection is enabled the brownout condition occurs when V ...
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... For any other reset, previously set flag bits that have not been cleared will remain set. P89LPC9351_1 Preliminary data sheet must fall below V DD POR Table 10 “Static characteristics”). Rev. 01 — 19 November 2008 P89LPC9351 8-bit microcontroller with 8-bit ADC before power is reapplied, in order © NXP B.V. 2008. All rights reserved ...
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... NXP Semiconductors 7.19.1 Reset vector Following reset, the P89LPC9351 will fetch instructions from either address 0000H or the Boot address. The Boot address is formed by using the boot vector as the high byte of the address and the low byte of the address = 00H. The boot address will be used if a UART break reset occurs, or the non-volatile boot status bit (BOOTSTAT ...
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... RTC/system timer The P89LPC9351 has a simple RTC that allows a user to continue running an accurate timer while the rest of the device is powered down. The RTC can be a wake- interrupt source. The RTC is a 23-bit down counter comprised of a 7-bit prescaler and a 16-bit loadable down counter. When it reaches all logic 0s, the counter will be reloaded again and the RTCF fl ...
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... Fig 7. P89LPC9351_1 Preliminary data sheet TOR2 compare value timer value 0x0000 non-inverted inverted Asymmetrical PWM, down-counting Rev. 01 — 19 November 2008 P89LPC9351 8-bit microcontroller with 8-bit ADC 002aaa893 © NXP B.V. 2008. All rights reserved ...
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... Symmetrical PWM Alternate output mode Equation 1: PCLK = ----------------- - Rev. 01 — 19 November 2008 P89LPC9351 8-bit microcontroller with 8-bit ADC 002aaa894 TOR2 COMPARE VALUE A (or C) COMPARE VALUE B (or D) TIMER VALUE 0 PWM OUTPUT (OCA or OCC) PWM OUTPUT (OCB or OCD) 002aaa895 © NXP B.V. 2008. All rights reserved. ...
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... TOCF2D (TIFR2.6) Fig 10. Capture/compare unit interrupts 7.23 UART The P89LPC9351 has an enhanced UART that is compatible with the conventional 80C51 UART except that Timer 2 overflow cannot be used as a baud rate source. The P89LPC9351 does include an independent baud rate generator. The baud rate can be selected from the oscillator (divided by a constant), Timer 1 overfl ...
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... Section 7.23.5 “Baud rate generator and 7.23.5 Baud rate generator and selection The P89LPC9351 enhanced UART has an independent baud rate generator. The baud rate is determined by a baud-rate preprogrammed into the BRGR1 and BRGR0 SFRs which together form a 16-bit baud rate divisor value that works in a similar manner as Timer 1 but is much more accurate ...
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... C-bus may be used for test and diagnostic purposes. 2 C-bus configuration is shown in 2 C-bus interface that supports data transfers up to 400 kHz. Rev. 01 — 19 November 2008 P89LPC9351 8-bit microcontroller with 8-bit ADC Figure 12. The P89LPC9351 device provides a © NXP B.V. 2008. All rights reserved ...
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... NXP Semiconductors Fig 12. I P89LPC9351_1 Preliminary data sheet 2 I C-bus P1.3/SDA P1.2/SCL P89LPC9351 2 C-bus configuration Rev. 01 — 19 November 2008 P89LPC9351 8-bit microcontroller with 8-bit ADC OTHER DEVICE OTHER DEVICE 2 2 WITH I C-BUS WITH I C-BUS INTERFACE INTERFACE 002aad731 © NXP B.V. 2008. All rights reserved. ...
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... FILTER OUTPUT STAGE timer 1 overflow P1.2 I2CON I2SCLH I2SCLL status bus I2STAT 2 C-bus serial interface block diagram Rev. 01 — 19 November 2008 P89LPC9351 8-bit microcontroller with 8-bit ADC 8 ADDRESS REGISTER I2ADR COMPARATOR SHIFT REGISTER ACK I2DAT 8 BIT COUNTER / ARBITRATION TIMING AND SYNC LOGIC ...
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... NXP Semiconductors 7.25 SPI The P89LPC9351 provides another high-speed serial communication interface: the SPI interface. SPI is a full-duplex, high-speed, synchronous communication bus with two operation modes: Master mode and Slave mode Mbit/s can be supported in either Master mode or Slave mode. It has a Transfer Completion Flag and Write Collision Flag Protection ...
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... REGISTER SPICLK SPI CLOCK PORT GENERATOR master MISO 8-BIT SHIFT MOSI REGISTER SPICLK SPI CLOCK SS GENERATOR Rev. 01 — 19 November 2008 P89LPC9351 8-bit microcontroller with 8-bit ADC slave MISO 8-BIT SHIFT MOSI REGISTER SPICLK SS 002aaa901 slave MISO 8-BIT SHIFT MOSI REGISTER SPICLK ...
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... Fig 17. SPI single master multiple slaves configuration 7.26 Analog comparators Two analog comparators are provided on the P89LPC9351. Input and output options allow use of the comparators in a number of different configurations. Comparator operation is such that the output is a logical one (which may be read in a register and/or routed to a pin) when the positive input (one of two selectable inputs) is greater than the negative input (selectable from a pin or an internal reference voltage) ...
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... P89LPC9351_1 Preliminary data sheet CP1 comparator 1 CO1 V ref(bg) CN1 CP2 comparator 2 CO2 CN2 10 %. Rev. 01 — 19 November 2008 P89LPC9351 8-bit microcontroller with 8-bit ADC OE1 CMP1 (P0.6) change detect CMF1 change detect CMF2 CMP2 (P0.0) OE2 002aad561 © NXP B.V. 2008. All rights reserved. interrupt EC ...
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... Watchdog mode. Feeding the watchdog requires a two-byte sequence. If PCLK is selected as the watchdog clock and the CPU is powered down, the watchdog is disabled. The watchdog timer has a time-out period that ranges from a few few seconds. Please refer to the P89LPC9351 User manual for more details. P89LPC9351_1 Preliminary data sheet Figure 19 Rev. 01 — ...
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... Data EEPROM The P89LPC9351 has 512 bytes of on-chip Data EEPROM. The Data EEPROM is SFR based, byte readable, byte writable, and erasable (via row fill and sector fill). The user can read, write and fill the memory via SFRs and one interrupt. This Data EEPROM provides 100,000 minimum erase/program cycles for each byte. • ...
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... Flash organization The program memory consists of eight 1 kB sectors on the P89LPC9351 devices. Each sector can be further divided into 64-byte pages. In addition to sector erase, page erase, and byte erase, a 64-byte page register is included which allows from 1 byte to 64 bytes of a given page to be programmed at the same time, substantially reducing overall programming time ...
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... ICP is performed without removing the microcontroller from the system. The ICP facility consists of internal hardware resources to facilitate remote programming of the P89LPC9351 through a two-wire serial interface. The NXP ICP facility has made in-circuit programming in an embedded application - using commercially available programmers - possible with a minimum of additional expense in components and circuit board area. The ICP function uses fi ...
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... Power-on reset code execution The P89LPC9351 contains two special flash elements: the Boot Vector and the Boot Status bit. Following reset, the P89LPC9351 examines the contents of the Boot Status bit. If the Boot Status bit is set to zero, power-up execution starts at location 0000H, which is the normal start address of the user’ ...
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... NXP Semiconductors 7.32 User sector security bytes There are eight User Sector Security Bytes on the P89LPC9351. Each byte corresponds to one sector. Please see the P89LPC9351 User manual for additional details. 8. ADC 8.1 General description The P89LPC9351 has two 8-bit, 4-channel multiplexed successive approximation analog-to-digital converter modules. Two high-speed programmable gain amplifi ...
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... PGAxTRIM2X4X and PGAxTRIM8X16X provide trim value of PGA gain level. As power-on, default trim value for each gain setting is loaded into the PGA trim registers. For accurate measurements, offset calibration is required. Please see the P89LPC9351 User manual for detail configuration, calibration, and usage information. 8.5 Temperature sensor An on-chip wide-temperature range temperature sensor is integrated with ADC0 module ...
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... ADxDAT0. The result of the conversion of the second channel is placed in result register, ADxDAT1. The first channel is again converted and its result stored in P89LPC9351_1 Preliminary data sheet Rev. 01 — 19 November 2008 P89LPC9351 8-bit microcontroller with 8-bit ADC © NXP B.V. 2008. All rights reserved ...
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... An interrupt will be generated, if enabled, if the result is outside the boundary limits. The boundary limit may be disabled by clearing the boundary limit interrupt enable. P89LPC9351_1 Preliminary data sheet Rev. 01 — 19 November 2008 P89LPC9351 8-bit microcontroller with 8-bit ADC © NXP B.V. 2008. All rights reserved ...
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... If the PGAs, temperature sensor or the A/D are enabled, they will consume power. Power can be reduced by disabling the PGA, temperature sensor and A/D. P89LPC9351_1 Preliminary data sheet Rev. 01 — 19 November 2008 P89LPC9351 8-bit microcontroller with 8-bit ADC © NXP B.V. 2008. All rights reserved ...
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... Parameters are valid over ambient temperature range unless otherwise specified. All voltages are with respect to V otherwise noted. P89LPC9351_1 Preliminary data sheet [1] Conditions except V , with respect transfer, not device power consumption Rev. 01 — 19 November 2008 P89LPC9351 8-bit microcontroller with 8-bit ADC Min Max 55 +125 65 +150 - 100 - 3 ...
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... V to 3.6 V; all ports, DD push-pull mode on XTAL1, XTAL2 pins; with respect except XTAL1, XTAL2 with respect 0 th(HL) Rev. 01 — 19 November 2008 P89LPC9351 8-bit microcontroller with 8-bit ADC [1] Min Typ Max [ [ [2] - 3. [2] ...
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... BOE1, BOE0 = 10 BOE1, BOE0 = 11 rising stage BOE1, BOE0 = 01 BOE1, BOE0 = 10 BOE1, BOE0 = 11 falling stage rising stage specifications are measured using an external clock with the following functions disabled: comparators, Rev. 01 — 19 November 2008 P89LPC9351 8-bit microcontroller with 8-bit ADC [1] Min Typ [ ...
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... Port pins source a transition current when used in quasi-bidirectional mode and externally driven from logic 1 to logic 0. This current is highest when V is approximately P89LPC9351_1 Preliminary data sheet Rev. 01 — 19 November 2008 P89LPC9351 8-bit microcontroller with 8-bit ADC © NXP B.V. 2008. All rights reserved ...
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... Figure 22 see Figure 22 see Figure 21 16T see Figure 21 13T see Figure 21 see Figure 21 see Figure 21 Rev. 01 — 19 November 2008 P89LPC9351 8-bit microcontroller with 8-bit ADC [1][2] Variable clock MHz osc Min Max Min 7.557 7.189 15.114 14.378 15.114 MHz 380 420 ...
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... Figure 23, 24, 25, 26 see Figure 23, 24, 25, 26 see Figure 23, 24, 25, 26 see Figure 23, 24, 25, 26 Rev. 01 — 19 November 2008 P89LPC9351 8-bit microcontroller with 8-bit ADC [1][2] Variable clock MHz osc Min Max Min - 500 CCLK - 333 CCLK 250 - 250 ...
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... Figure 22 see Figure 21 see Figure 21 see Figure 21 see Figure 21 see Figure 21 see Figure 23, 24, 25, 26 Rev. 01 — 19 November 2008 P89LPC9351 8-bit microcontroller with 8-bit ADC [1][2] Variable clock f osc Min Max Min 7.189 7.557 7.189 14.378 15.114 14.378 15.114 MHz 380 420 ...
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... Figure 25, 26 see Figure 23, 24, 25, 26 see Figure 23, 24, 25, 26 see Figure 23, 24, 25, 26 see Figure 23, 24, 25, 26 Rev. 01 — 19 November 2008 P89LPC9351 8-bit microcontroller with 8-bit ADC [1][2] Variable clock f osc Min Max Min 250 - 250 250 - 250 3 - 167 CCLK 2 - ...
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... SPICLKH t t SPIF SPIR t SPICLKL t SPICLKH t t SPIDSU SPIDH MSB/LSB SPIDV SPIOH master MSB/LSB out Rev. 01 — 19 November 2008 P89LPC9351 8-bit microcontroller with 8-bit ADC valid valid valid t CHCX t CLCH T cy(clk) 002aaa907 = 200 mV) t SPIR LSB/MSB in t SPIDV master LSB/MSB out ...
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... SPIR t SPICLKL t SPICLKH t t SPIOH SPIOH t t SPIDV SPIDV slave MSB/LSB out t t SPIDH SPIDSU MSB/LSB in Rev. 01 — 19 November 2008 P89LPC9351 8-bit microcontroller with 8-bit ADC t SPIR LSB/MSB SPIDV SPIDV t SPIR master LSB/MSB out 002aaa909 t SPIR t SPILAG t t SPIOH SPIDIS ...
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... MSB/LSB out SPIDSU SPIDH SPIDSU MSB/LSB in Conditions pin RST pin RST RST t RL Rev. 01 — 19 November 2008 P89LPC9351 8-bit microcontroller with 8-bit ADC t SPIR t SPILAG t SPIDIS slave LSB/MSB out t t SPIDSU SPIDH LSB/MSB in 002aaa911 Min Typ Max ...
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... This parameter is characterized, but not tested in production. P89LPC9351_1 Preliminary data sheet Conditions Min - 0 [ < V < Rev. 01 — 19 November 2008 P89LPC9351 8-bit microcontroller with 8-bit ADC Typ Max - 0 250 500 - © NXP B.V. 2008. All rights reserved. ...
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... ADC enabled - within accuracy - of ADC 14. amb - Rev. 01 — 19 November 2008 P89LPC9351 8-bit microcontroller with 8-bit ADC Typ Max 0 0 100 - 2000 - 13T cy(ADC 1.00 1 ...
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... H D 0.81 11.58 11.58 10.92 10.92 12.57 1.27 0.66 11.43 11.43 9.91 9.91 12.32 0.032 0.456 0.456 0.43 0.43 0.495 0.05 0.026 0.450 0.450 0.39 0.39 0.485 REFERENCES JEDEC JEITA MS-018 EDR-7319 Rev. 01 — 19 November 2008 P89LPC9351 8-bit microcontroller with 8-bit ADC detail ( max. 12.57 1.22 1.44 ...
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... Preliminary data sheet 2.5 scale (1) ( 0.30 0.2 9.8 4.5 0.65 0.19 0.1 9.6 4.3 REFERENCES JEDEC JEITA MO-153 Rev. 01 — 19 November 2008 P89LPC9351 8-bit microcontroller with 8-bit ADC detail 6.6 0.75 0.4 1 0.2 0.13 6.2 0.50 0.3 EUROPEAN PROJECTION ...
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... Programmable Gain Amplifier Phase-Locked Loop Pulse Width Modulator Random Access Memory Resistance-Capacitance Real-Time Clock Successive Approximation Register Special Function Register Serial Peripheral Interface Universal Asynchronous Receiver/Transmitter Rev. 01 — 19 November 2008 P89LPC9351 8-bit microcontroller with 8-bit ADC © NXP B.V. 2008. All rights reserved ...
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... NXP Semiconductors 15. Revision history Table 17. Revision history Document ID Release date P89LPC9351_1 20081119 P89LPC9351_1 Preliminary data sheet Data sheet status Change notice Preliminary data sheet - Rev. 01 — 19 November 2008 P89LPC9351 8-bit microcontroller with 8-bit ADC Supersedes - © NXP B.V. 2008. All rights reserved ...
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... Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners C-bus — logo is a trademark of NXP B.V. http://www.nxp.com salesaddresses@nxp.com Rev. 01 — 19 November 2008 P89LPC9351 8-bit microcontroller with 8-bit ADC © NXP B.V. 2008. All rights reserved ...
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... Comparators and power reduction modes . . . 44 7.27 KBI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 7.28 Watchdog timer . . . . . . . . . . . . . . . . . . . . . . . 45 7.29 Additional features . . . . . . . . . . . . . . . . . . . . . 46 7.29.1 Software reset . . . . . . . . . . . . . . . . . . . . . . . . 46 7.29.2 Dual data pointers . . . . . . . . . . . . . . . . . . . . . 46 7.29.3 Data EEPROM . . . . . . . . . . . . . . . . . . . . . . . . 46 7.30 Flash program memory . . . . . . . . . . . . . . . . . 47 Rev. 01 — 19 November 2008 P89LPC9351 8-bit microcontroller with 8-bit ADC bit (bit 8) in double buffering continued >> © NXP B.V. 2008. All rights reserved ...
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... Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2008. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com All rights reserved. Date of release: 19 November 2008 Document identifier: P89LPC9351_1 ...