p89lpc932ba NXP Semiconductors, p89lpc932ba Datasheet - Page 20

• Manufacturer Part Number: p89lpc932ba
• Description: P89lpc932 8-bit Microcontroller With Accelerated Two-clock 80c51 Core 8 Kb Flash With 512-byte Data Eeprom And 768-byte Ram
• Manufacturer: NXP Semiconductors

Philips Semiconductors
9397 750 12379
Product data
8.11.1 External interrupt inputs
8.10 Data RAM arrangement
8.11 Interrupts
The P89LPC932 also has 512 bytes of on-chip Data EEPROM that is accessed via
SFRs (see
The 768 bytes of on-chip RAM are organized as shown in
Table 5:
The P89LPC932 uses a four priority level interrupt structure. This allows great
flexibility in controlling the handling of the many interrupt sources. The P89LPC932
supports 15 interrupt sources: external interrupts 0 and 1, timers 0 and 1, serial port
Tx, serial port Rx, combined serial port Rx/Tx, brownout detect, watchdog/Real-Time
clock, I
completion.
Each interrupt source can be individually enabled or disabled by setting or clearing a
bit in the interrupt enable registers IEN0 or IEN1. The IEN0 register also contains a
global disable bit, EA, which disables all interrupts.
Each interrupt source can be individually programmed to one of four priority levels by
setting or clearing bits in the interrupt priority registers IP0, IP0H, IP1, and IP1H. An
interrupt service routine in progress can be interrupted by a higher priority interrupt,
but not by another interrupt of the same or lower priority. The highest priority interrupt
service cannot be interrupted by any other interrupt source. If two requests of
different priority levels are pending at the start of an instruction, the request of higher
priority level is serviced.
If requests of the same priority level are pending at the start of an instruction, an
internal polling sequence determines which request is serviced. This is called the
arbitration ranking. Note that the arbitration ranking is only used to resolve pending
requests of the same priority level.
The P89LPC932 has two external interrupt inputs as well as the Keypad Interrupt
function. The two interrupt inputs are identical to those present on the standard
80C51 microcontrollers.
These external interrupts can be programmed to be level-triggered or edge-triggered
by setting or clearing bit IT1 or IT0 in Register TCON.
In edge-triggered mode, if successive samples of the INTn pin show a HIGH in one
cycle and a LOW in the next cycle, the interrupt request flag IEn in TCON is set,
causing an interrupt request.
Type
DATA
IDATA
XDATA
2
C, keyboard, comparators 1 and 2, SPI, CCU, data EEPROM write
On-chip data memory usages
Section 8.26 “Data
Data RAM
Memory that can be addressed directly and indirectly
Memory that can be addressed indirectly
Auxiliary (‘External Data’) on-chip memory that is accessed
using the MOVX instructions
Rev. 04 — 06 January 2004
8-bit microcontroller with accelerated two-clock 80C51 core
EEPROM”).
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Table
P89LPC932
5.
Size (bytes)
128
256
512
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