p89lpc932ba NXP Semiconductors, p89lpc932ba Datasheet - Page 19

• Manufacturer Part Number: p89lpc932ba
• Description: P89lpc932 8-bit Microcontroller With Accelerated Two-clock 80c51 Core 8 Kb Flash With 512-byte Data Eeprom And 768-byte Ram
• Manufacturer: NXP Semiconductors

Philips Semiconductors
9397 750 12379
Product data
8.6 CPU Clock (CCLK) wake-up delay
8.7 CPU Clock (CCLK) modification: DIVM register
8.8 Low power select
8.9 Memory organization
The P89LPC932 has an internal wake-up timer that delays the clock until it stabilizes
depending on the clock source used. If the clock source is any of the three crystal
selections (low, medium and high frequencies) the delay is 992 OSCCLK cycles plus
60 to 100 s. If the clock source is either the internal RC oscillator, watchdog
oscillator, or external clock, the delay is 224 OSCCLK cycles plus 60 to 100 s.
The OSCCLK frequency can be divided down up to 510 times by configuring a
dividing register, DIVM, to generate CCLK. This feature makes it possible to
temporarily run the CPU at a lower rate, reducing power consumption. By dividing the
clock, the CPU can retain the ability to respond to events that would not exit Idle
mode by executing its normal program at a lower rate. This can also allow bypassing
the oscillator start-up time in cases where Power-down mode would otherwise be
used. The value of DIVM may be changed by the program at any time without
interrupting code execution.
The P89LPC932 is designed to run at 12 MHz (CCLK) maximum. However, if CCLK
is 8 MHz or slower, the CLKLP SFR bit (AUXR1.7) can be set to ‘1’ to lower the power
consumption further. On any reset, CLKLP is ‘0’ allowing highest performance
access. This bit can then be set in software if CCLK is running at 8 MHz or slower.
The various P89LPC932 memory spaces are as follows:
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DATA
128 bytes of internal data memory space (00h:7Fh) accessed via direct or indirect
addressing, using instructions other than MOVX and MOVC. All or part of the
Stack may be in this area.
IDATA
Indirect Data. 256 bytes of internal data memory space (00h:FFh) accessed via
indirect addressing using instructions other than MOVX and MOVC. All or part of
the Stack may be in this area. This area includes the DATA area and the 128 bytes
immediately above it.
SFR
Special Function Registers. Selected CPU registers and peripheral control and
status registers, accessible only via direct addressing.
XDATA
‘External’ Data or Auxiliary RAM. Duplicates the classic 80C51 64 kB memory
space addressed via the MOVX instruction using the SPTR, R0, or R1. All or part
of this space could be implemented on-chip. The P89LPC932 has 512 bytes of
on-chip XDATA memory.
CODE
64 kB of Code memory space, accessed as part of program execution and via the
MOVC instruction. The P89LPC932 has 8 kB of on-chip Code memory.
Rev. 04 — 06 January 2004
8-bit microcontroller with accelerated two-clock 80C51 core
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
P89LPC932
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