pxf4333 Infineon Technologies Corporation, pxf4333 Datasheet - Page 192

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pxf4333

Manufacturer Part Number
pxf4333
Description
Abm 3g Atm Buf Fer Manager
Manufacturer
Infineon Technologies Corporation
Datasheet
Register 30 LCI0
CPU Accessibility:
Reset Value:
Offset Address:
Typical Usage:
Bit
Bit
CLPT
ABMcore
Data Sheet
15
7
LCI Transfer Register 0
14
CLP Transparent:
Specifies whether the CLP bit of cells belonging to this connection
is evaluated or not in threshold checks. Valid for both upstream and
downstream cores. Does not affect SBOC counters.
0
1
ABM-3G Core Selection:
This bit is valid in Uni-directional Mode only and specifies the core
responsible for cells of this LCI.
0
1
6
Read/Write
0000
LCI0
Written and Read by CPU to maintain the LCI table
H
13
Unused(5:0)
5
CLP bit is evaluated.
CLP bit is not evaluated; all cells are treated as high
priority cells assuming CLP=0.
Scheduler Blocks 0..127 are selected (core 0).
Scheduler Blocks 128..255 are selected (core 1).
3B
H
Unused(13:6)
12
4
192
11
3
10
2
Register Description
CLPT
PXF 4333 V1.1
9
1
2001-12-17
ABM-3G
ABM
core
8
0

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