zl2103 Intersil Corporation, zl2103 Datasheet - Page 2

• Manufacturer Part Number: zl2103
• Description: 3a Digital-dc Synchronous Step-down Dc/dc Converter
• Manufacturer: Intersil Corporation

Typical Application Circuit
The following application circuit represents a typical
implementation of the ZL2103. For PMBus operation, it is
recommended to tie the enable pin (EN) to SGND.
Block Diagram
DDC Bus
SMBus
ENABLE
PGOOD
Notes:
‡
†
connected. The 10 k♦ default value, assuming a maximum of 100 pF per device, provides the necessary 1 µs pull-up rise
time. Please refer to the Digital-DC Bus section for more details.
††
connected. Please refer to the I
I
The DDC bus pull-up resistance will vary based on the capacitive loading of the bus, including the number of devices
Ferrite bead is optional for input noise suppression.
2
The I
C/
2
††
C/SMBus pull-up resistance will vary based on the capacitive loading of the bus, including the number of devices
†
FIGURE 2. 12V TO 3.3V/3A APPLICATION CIRCUIT (5ms SS DELAY, 5ms SS RAMP)
2
VTRK
VSET
CFG
Ω
MGN
DDC
SS
PG
EN
SA
V
IN
2
1
2
3
4
5
6
7
8
9
DDC Bus
C/SMBus specifications for more details.
2.5V
LDO
Power
Mgmt
SMBus
SA
PG
DGND
SYNC
VSET
SCL
SDA
SALRT
FC
LDO
10µF
5V
C
FIGURE 3. BLOCK DIAGRAM
NVM
25
Control
Drivers
PWM
ZL2103
&
ZL2103
4.7µF
LDO
C
7V
RA
4.7µF
C
R
PGND
VDDP
F.B.
BST
SW
SW
SW
SW
SW
SW
VSEN
BST
‡
SW
19
27
26
25
24
23
22
21
20
47nF
2.2µF
C
C
B
DD
V
100µF
OUT
150µF
C
2.2µH
C
L
IN
OUT
OUT
12V
V
IN
V
3.3V
OUT
May 3, 2011
FN6966.5