zl2106 Intersil Corporation, zl2106 Datasheet - Page 18

• Manufacturer Part Number: zl2106
• Description: 6a Digital-dc Synchronous Step-down Dc-dc Converter
• Manufacturer: Intersil Corporation

6.6 Power Good (PG)
The ZL2106 provides a Power Good (PG) signal that
indicates the output voltage is within a specified
tolerance of its target level and no fault condition
exists. By default, the PG pin will assert if the output is
within +15%/-10% of the target voltage. These limits
may be changed via the I
Application Note AN33 for details.
A PG delay period is the time from when all conditions
for asserting PG are met and when the PG pin is
actually asserted. This feature is commonly used
instead of an external reset controller to signal the
power supply is at its target voltage prior to enabling
any powered circuitry. By default, the ZL2106 PG
delay is set to 1 ms and may be changed using the
I
6.7 Switching Frequency and PLL
The ZL2106 incorporates an internal phase-locked
loop (PLL) to clock the internal circuitry. The PLL can
be driven by an external clock source connected to the
SYNC pin. When using the internal oscillator, the
SYNC pin can be configured as a clock source for
other Zilker Labs devices.
2
C/SMBus interface as described in AN33.
18
2
C/SMBus interface. See
Figure 15. SYNC Pin Configurations
ZL2106
The SYNC pin is a unique pin that can perform
multiple functions depending on how it is configured.
The CFG pin is used to select the operating mode of
the SYNC pin as shown in Table 11. Figure 15
illustrates the typical connections for each mode.
Table 11. SYNC Pin Function Selection
Configuration A: SYNC OUTPUT
When the SYNC pin is configured as an output (CFG
pin is tied HIGH), the device will run from its internal
oscillator and will drive the resulting internal oscillator
signal (preset to 400 kHz) onto the SYNC pin so other
devices can be synchronized to it. The SYNC pin will
not be checked for an incoming clock signal while in
this mode.
Configuration B: SYNC INPUT
When the SYNC pin is configured as an input (CFG
pin is tied LOW), the device will automatically check
for an external clock signal on the SYNC pin each time
CFG Pin
OPEN
HIGH
LOW
SYNC is configured as an input
Auto detect mode
SYNC is configured as an output f
400 kHz
SYNC Pin Function
Data Sheet Revision 2/19/2009
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