l6706 STMicroelectronics, l6706 Datasheet - Page 8

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l6706

Manufacturer Part Number
l6706
Description
Vr11.1 Single Phase Controller With Integrated Driver
Manufacturer
STMicroelectronics
Datasheet

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Pins description and connection diagrams
8/47
Table 2.
20 to 27
16
17
18
19
28
29
30
31
32
33
34
35
36
37
38
OUTEN
VCCDR
SSEND
PHASE
VID0 to
LGATE
PGND
Name
VID7
INT1
INT2
INT3
INT4
CS+
N.C.
N.C.
N.C.
CS-
Pin description (continued)
Output enable pin.
Internally pulled up by 10 µA (typ) to 3 V. Forced low, the device stops
operations with all MOSFETs OFF: all the protections are disabled except for
preliminary over voltage. Leave floating, the device starts-up implementing soft-
start up to the selected VID code. Cycle this pin to recover latch from
protections; filter with 1 nF (typ) vs. SGND.
Current sense positive input.
Connect through an R-C filter to the phase-side of the output inductor.
See
connection.
Current sense negative input.
Connect through a Rg resistor to the output-side of the output inductor.
See
connection.
Test mode pin.
It must be left unconnected or connected to 3.3 V.
Voltage identification pins. (not internally pulled up).
Connect to SGND to program a '0' or connect to the external Pull-up resistor to
program a '1'. They allow programming output voltage as specified in
Test mode pin.
It must be connected to SGND.
Soft-start end signal.
Open drain output sets free after SS has finished and pulled low when
triggering any protection. Pull up to a voltage lower than 3.3 V, if not used it can
be left floating.
Not internally connected.
Test mode pin.
It must be connected to 12 V.
Not internally connected.
Test mode pin.
It must be connected to 12 V.
Not internally connected.
LS driver supply.
VCDDR pin voltage has to be the same of VCC pin.
Filter with 1 x 1 µF MLCC capacitor vs. PGND.
LS driver output.
A small series resistor helps in reducing device-dissipated power.
Power ground pin (LS drivers return path).
Connect to power ground plane.
HS driver return path.
It must be connected to the HS MOSFET source and provides return path for
the HS driver.
Section 20: Layout guidelines on page 43
Section 20: Layout guidelines on page 43
Doc ID 15698 Rev 1
Description
for proper layout of this
for proper layout of this
Table 7.
L6706

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