W83977AF Information Storage Devices, Inc, W83977AF Datasheet - Page 71

• Manufacturer Part Number: W83977AF
• Description: W83877TF Plus Kbc, Cir, RTC
• Manufacturer: Information Storage Devices, Inc

Bit 2:
Bit 1, 0:
4.2.6 Set0.Reg5 - IR Status Register (USR)
Legacy IR Register: These registers are defined the same as previous description.
Advanced IR Register:
Bit 7:
Bit 6, 5:
Bit 4:
Bit 3:
Bit 2:
Bit 1, 0:
4.2.7 Set0.Reg6 - Reserved
4.2.8 Set0.Reg7 - User Defined Register (UDR/AUDR)
Legacy IR
Advanced
Reset Value
Advanced IR LB_INFR
Legacy IR
Reset Value
Mode
Mode
IR
MIR, FIR modes:
Other modes: Not used.
MIR, FIR Modes:
MIR, FIR modes:
MIR, FIR modes:
MIR, FIR Modes:
FLC_ACT UNDRN
EN_DMA - Enable DMA
Enable DMA function for transmitting or receiving. Before using this, the DMA channel
should be selected first. If only RX DMA channel is set and TX DMA channel is disabled,
then the single DMA channel is used. In the single channel system, the bit of D_CHSW
(DMA channel swap, in Set 2.Reg2.Bit3) will determine if it is RX_DMA or TX_DMA
channel.
RTS, DTR
Functional definitions is the same as in legacy IR mode.
LB_INFR - Last Byte In Frame End
Set to 1 when last byte of a frame is in the bottom of FIFO. This bit separates one frame
from another when RX FIFO has more than one frame.
Same as legacy IR description.
MX_LEX - Maximum Frame Length Exceed
Set to 1 when the length of a frame from the receiver has exceeded the programmed
frame length defined in SET4.Reg6 and Reg5. If this bit is set to 1, the receiver will not
receive any data to RX FIFO.
PHY_ERR - Physical Layer Error
Set to 1 when an illegal data symbol is received. The illegal data symbol is defined in
physical layer of IrDA version 1.1. When this bit is set to 1, the decoder of receiver will
be aborted and a frame end signal is set to 1.
CRC_ERR - CRC Error
Set to 1 when an attached CRC is erroneous.
OER - Overrun Error, RDR - RBR Data Ready
Definitions are the same as legacy IR.
Bit 7
Bit 7
0
RFEI
B7
0
Bit 6
Bit 6
0
TSRE
TSRE
B6
0
RX_BSY/
RX_IP
Bit 5
Bit 5
TBRE
TBRE
0
B5
0
- 59 -
LST_FE/
MX_LEX PHY_ERR CRC_ERR
RX_PD
Bit 4
Bit 4
SBD
B4
0
0
W83977F/ W83977AF
S_FEND
NSER
Bit 3
Bit 3
Publication Release Date: March 1998
B3
0
0
Bit 2
PBER
Bit 2
B2
0
0
0
PRELIMINARY
LB_SF
Bit 1
Bit 1
OER
OER
B1
0
0
Revision 0.58
RX_TO
Bit 0
Bit 0
RDR
RDR
B0
0
0