r2j20652anp Renesas Electronics Corporation., r2j20652anp Datasheet - Page 12

• Manufacturer Part Number: r2j20652anp
• Description: Integrated Driver ? Mos Fet Drmos
• Manufacturer: Renesas Electronics Corporation.

R2J20652ANP
Description of Operation
The DrMOS multi-chip module incorporates a high-side MOS FET, low-side MOS FET, and MOS-FET driver in a
single QFN package. Since the parasitic inductance between each chip is extremely small, the module is highly suitable
for use in buck converters to be operated at high frequencies. The control timing between the high-side MOS FET, low-
side MOS FET, and driver is optimized so that high efficiency can be obtained at low output-voltage.
VCIN & DISBL#
The VCIN pin is connected to the UVL (under-voltage lockout) module, so that the built-in 5 V regulator is disabled as
long as VCIN is 7.4 V or less. On cancellation of UVL, the built-in 5 V regulator remains enabled until the UVL input
is driven to 7.0 V or less.
The built-in 5 V regulator is a series regulator with temperature compensation. A ceramic capacitor with a value of 0.1
F or more must be connected between the CGND plane and the Reg5V Pin.
The output of 5 V regulator is monitored by the internal Supervisor circuits. When the Supervisor detects this output is
more than 4.2 V (typ.), the driver state becomes active (figure1.1).
Figure 1.2 shows the application when the external 5 V regulator is used. When the Reg5V pin is applied into external 5
V, the Supervisor can activate the driver. In this application usage, VCIN should be connected to Reg5V.
The signal on pin DISBL# also enables or disables the circuit. When UVL disables the circuit, the built-in 5 V regulator
does not operate, but when the signal on DISBL# disables the circuit, only output-pulse generation is terminated, and
the 5 V regulator is not disabled.
Voltages from –0.3 V to VCIN + 0.3 V can be applied to the DISBL# pin, so on/off control by a logic IC or the use of a
resistor, etc., to pull the DISBL# line up to VCIN are both possible.
REJ03G1867-0300 Rev.3.00 Feb 26, 2010
Page 12 of 16
VCIN
H
H
H
L
Figure 1.1 Typical 12 V Input Application
(Activate Built-in 5 V Regulator)
To Internal
DISBL#
Logic
Open
H

L
5 V Regulator
Supervisor
UVL &
12 V
IN
VCIN
REG5V
Active
Active
Active
VCIN > 7.4 V
0
Reg5V
Disable (GL, GH = L)
Disable (GL, GH = L)
Active
Disable (GL, GH = L)
Driver State
To Internal
Logic
Figure 1.2 External 5 V Application
5 V Regulator
Supervisor
UVL &
IN
VCIN
Reg5V
External 5 V
Preliminary
5 V