x9523v20iz-bt1 Intersil Corporation, x9523v20iz-bt1 Datasheet - Page 8

• Manufacturer Part Number: x9523v20iz-bt1
• Description: Dual Dcp, Por, Dual Voltage Monitors
• Manufacturer: Intersil Corporation

WCR and NVM. Therefore, the new “wiper position” set-
ting is recalled into the WCR after V1/Vcc of the X9523
has been powered down then powered back up.
If WT is “0” then a DCP Volatile Write is performed. This
operation changes the DCP “wiper position” by writing
new data to the associated WCR only. The contents of
the associated NVM register remains unchanged. There-
fore, when V1/Vcc to the device is powered down then
back up, the “wiper position” reverts to that last written to
the DCP using a nonvolatile write operation.
DCP Write Operation
A write to DCPx (x = 1,2) can be performed using the
three byte command sequence shown in Figure 9.
In order to perform a write operation on a particular DCP,
the Write Enable Latch (WEL) bit of the CONSTAT Reg-
ister must first be set (See “WEL: Write Enable Latch
(Volatile)” on page 10.).
The Slave Address Byte 10101110 specifies that a Write
to a DCP is to be conducted. An ACKNOWLEDGE is
returned by the X9523 after the Slave Address, if it has
been received correctly.
†
WT
This bit has no effect when a Read operation is being performed.
0
1
WRITE TYPE
†
S
T
A
R
T
Figure 8.
Select a Volatile Write operation to be performed
on the DCP pointed to by bits P1 and P0
Select a Nonvolatile Write operation to be per-
formed on the DCP pointed to by bits P1 and P0
I7
WT
1
0
I6
SLAVE ADDRESS BYTE
0
1
I5
0
Instruction Byte Format
0
I4
1
0
Description
Figure 9.
8
1
I3
0
1
I2
0
0
DCP SELECT
DCP Write Command Sequence
I1
A
C
K
P1
WT
I0
P0
0
INSTRUCTION BYTE
0
0
X9523
0
0
Next, an Instruction Byte is issued on SDA. Bits P1 and
P0 of the Instruction Byte determine which WCR is to be
written, while the WT bit determines if the Write is to be
volatile or nonvolatile. If the Instruction Byte format is
valid, another ACKNOWLEDGE is then returned by the
X9523.
Following the Instruction Byte, a Data Byte is issued to
the X9523 over SDA. The Data Byte contents is latched
into the WCR of the DCP on the first rising edge of the
clock signal, after the LSB of the Data Byte (D0) has
been issued on SDA (See Figure 29).
The Data Byte determines the “wiper position” (which
FET switch of the DCP resistive array is switched ON) of
the DCP. The maximum value for the Data Byte depends
upon which DCP is being addressed (see Table below).
Using a Data Byte larger than the values specified above
results in the “wiper terminal” being set to the highest tap
position. The “wiper position” does NOT roll-over to the
lowest tap position.
For DCP2 (256 Tap), the Data Byte maps one to one to
the “wiper position” of the DCP “wiper terminal”. There-
fore, the Data Byte 00001111 (15
ting the “wiper terminal” to tap position 15. Similarly, the
Data Byte 00011100 (28
“wiper terminal” to tap position 28. The mapping of the
Data Byte to “wiper position” data for DCP1 (100 Tap), is
shown in “APPENDIX 1”. An example of a simple C lan-
guage function which “translates” between the tap posi-
tion (decimal) and the Data Byte (binary) for DCP1, is
given in “APPENDIX 2”.
P1 P0
P1- P0
0
0
1
1
0
1
0
1
A
C
K
DCPx
D7 D6 D5 D4 D3 D2 D1 D0
x = 1
x = 2
DATA BYTE
# Taps
10
100
256
) corresponds to setting the
RESERVED
RESERVED
10
) corresponds to set-
Refer to Appendix 1
Max. Data Byte
FFh
A
C
K
January 3, 2006
S
T
O
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FN8209.1