x9523v20iz-bt1 Intersil Corporation, x9523v20iz-bt1 Datasheet - Page 6

• Manufacturer Part Number: x9523v20iz-bt1
• Description: Dual Dcp, Por, Dual Voltage Monitors
• Manufacturer: Intersil Corporation

final STOP condition), the X9523 initiates an internal high
voltage write cycle. This cycle typically requires 5 ms.
During this time, no further Read or Write commands can
be issued to the device. Write Acknowledge Polling is
used to determine when this high voltage write cycle has
been completed.
To perform acknowledge polling, the master issues a
START condition followed by a Slave Address Byte. The
Slave Address issued must contain a valid Internal
Device Address. The LSB of the Slave Address (R/W)
can be set to either 1 or 0 in this case. If the device is still
busy
ACKNOWLEDGE will be returned. If the device has
completed the write operation, an ACKNOWLEDGE will
be returned and the host can then proceed with a read or
write operation. (Refer to Figure 5.).
Figure 5.
with
command sequence?
Issue Slave Address
Byte (Read or Write)
Byte load completed
High Voltage Cycle
complete. Continue
command sequence
Enter ACK Polling
by issuing STOP.
Continue normal
Issue START
Read or Write
PROCEED
the
returned?
Acknowledge Polling Sequence
ACK
high
YES
YES
6
voltage
NO
NO
cycle
Issue STOP
Issue STOP
then
no
X9523
DIGITALLY CONTROLLED POTENTIOMETERS
DCP Functionality
The X9523 includes two independent resistor arrays.
These arrays respectively contain 99 and 255 discrete
resistive segments that are connected in series. The
physical ends of each array are equivalent to the fixed
terminals of a mechanical potentiometer (R
inputs - where x = 1,2).
At both ends of each array and between each resistor
segment there is a CMOS switch connected to the wiper
(R w
switch may be turned on at any one time. These
switches are controlled by the Wiper Counter Register
(WCR) (See Figure 6). The WCR is a volatile register.
On power-up of the X9523, wiper position data is auto-
matically loaded into the WCR from its associated Non
Volatile Memory (NVM) Register. The Table below
shows the Initial Values of the DCP WCR’s before the
contents of the NVM is loaded into the WCR.
REGISTER
COUNTER
VOLATILE
MEMORY
WIPER
x
(NVM)
(WCR)
R
R
NON
) output. Within each individual array, only one
Figure 6.
1
2
/ 100 TAP
/ 256 TAP
DCP
DECODER
DCP Internal Structure
Initial Values Before Recall
N
2
1
0
V
V
H
SWITCHES
L
/ TAP = 255
“WIPER”
/ TAP = 0
FET
RESISTOR
ARRAY
Hx
January 3, 2006
and R
FN8209.1
R
R
R
Hx
Lx
Wx
Lx