dm9302 Davicom Semiconductor, Inc., dm9302 Datasheet - Page 49

• Manufacturer Part Number: dm9302
• Description: 10/100mbps Ethernet Fiber/twisted Pair Media Converter With Local Bus
• Manufacturer: Davicom Semiconductor, Inc.

9.2 Switch function:
learning the MAC addresses of incoming packets in
real time. DM9302 stores MAC addresses, port
number
Hash-based Address Table. It can learn up to 1K
unicast address entry.
new entry if incoming packet’s Source Address (SA)
does not exist and incoming packet is valid (non-error
and legal length).
address learning for individual port. This feature can
be set by bit 0 of register 65h
used in the aging process. The switch engine
updates time stamp whenever the corresponding SA
receives. The switch engine would delete the entry if
its time stamp is not updated for a period of time.
bit 0 & 1 of register 52h.
according to following decision:
forwarded to all ports, except to the port on which the
packet was received.
based on DA when incoming packets is UNICAST. If
the DA was not found in address table, the packet is
treated as a multicast packet and forward to other
ports. If the DA was found and its destination port
number is different to source port number, the packet
is forward to destination port.
Monitor setting and other forwarding constraints for
the forwarding decision, more detail will discuss in
later sections.
following conditions:
alignment errors, illegal size errors.
Preliminary datasheet
DM9302-15-DS-P01
July 30, 2009
The period can be programmed or disabled through
9.2.1 Address Learning
9.2.2 Address Aging
9.2.3 Packet Forwarding
The DM9302 has a self-learning mechanism for
The switch engine updates address table with
Besides, DM9302 has an option to disable
The time stamp information of address table is
The DM9302 forwards the incoming packet
(1). If DA is Multicast/Broadcast, the packet is
(2). Switch engine would look up address table
(3). Switch engine also look up VLAN, Port
The DM9302 will filter incoming packets under
(1).
(2). PAUSE packets.
(3). If incoming packet is UNICAST and its
Error
and
time
packets,
stamp
including
10/100Mbps Ethernet Fiber/Twisted Pair Media Converter with Local bus
information
CRC
in
errors,
the
destination port number is equal to source port
number.
at the same port. The typical number is 96 bits time.
In other word, the value is 9.6u sec for 10Mbps and
960n sec for 100Mbps.
back-off algorithm in half-duplex mode compliant to
IEEE standard 802.3.
error occurs after the first 512 bit times of data are
transmitted, the packet is dropped.
control frames on both transmit and receive sides.
transmitting next normal frames, if it receives a pause
frame from link partner.
frame with maximum pause time when internal
resources such as received buffers, transmit queue
and transmit descriptor ring are unavailable. Once
resources are available, The DM9302 sends out a
pause frame with zero pause time allows traffic to
resume immediately.
The inducement is the same as full duplex mode.
When flow control is required, the DM9302 sends jam
pattern, thus forcing a collision.
register 61h.
port, see bit 6 of register 61h. The port enters
partition mode when more than 64 consecutive
collisions are occurred. In partition mode the port
continuous to transmit but it will not receive. The port
returned to normal operation mode when a good
9.2.4 Inter-Packet Gap (IPG)
9.2.5 Back-off Algorithm
9.2.6 Late Collision
9.2.7 Half Duplex Flow Control
9.2.8 Full Duplex Flow Control
9.2.9 Partition Mode
IPG is the idle time between any two valid packets
The DM9302 implements the binary exponential
Late Collision is a type of collision. If a collision
The DM9302 supports IEEE standard 802.3x flow
On the receive side, The DM9302 will defer
On the transmit side, The DM9302 issues pause
The DM9302 supports half-duplex backpressure.
The flow control ability can be set in bit 4 of
The DM9302 provides a partition mode for each
DM9302
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