dm9302 Davicom Semiconductor, Inc., dm9302 Datasheet - Page 44

• Manufacturer Part Number: dm9302
• Description: 10/100mbps Ethernet Fiber/twisted Pair Media Converter With Local Bus
• Manufacturer: Davicom Semiconductor, Inc.

8.9 DAVICOM Specified Configuration and Status Register (DSCSR) – 11H
8-4 PHYADR[4:0] 1, RW PHY Address Bit 4:0
3-0
Bit
15
14
13
12
11
10
44
9
0
ANMB[3:0]
Bit Name
Reserved
Reserved
Reserved
100HDX
100FDX
10HDX
10FDX
RLOUT
Default
1, RO 100M Full Duplex Operation Mode
1, RO 100M Half Duplex Operation Mode
1, RO 10M Full Duplex Operation Mode
1, RO 10M Half Duplex Operation Mode
0, RO Reserved
0, RO
0,RW Reserved
0,RW Reserved
After auto-negotiation is completed, results will be written to this bit. If this bit is 1, it
means the operation 1 mode is a 100M full duplex mode. The software can read bit
[15:12] to see which mode is selected after auto-negotiation. This bit is invalid when
it is not in the auto-negotiation mode
After auto-negotiation is completed, results will be written to this bit. If this bit is 1, it
means the operation 1 mode is a 100M half duplex mode. The software can read bit
[15:12] to see which mode is selected after auto-negotiation. This bit is invalid when
it is not in the auto-negotiation mode
After auto-negotiation is completed, results will be written to this bit. If this bit is 1, it
means the operation 1 mode is a 10M Full Duplex mode. The software can read bit
[15:12] to see which mode is selected after auto-negotiation. This bit is invalid when
it is not in the auto-negotiation mode
After auto-negotiation is completed, results will be written to this bit. If this bit is 1, it
means the operation 1 mode is a 10M half duplex mode. The software can read bit
[15:12] to see which mode is selected after auto-negotiation. This bit is invalid when
it is not in the auto-negotiation mode
Read as 0, ignore on write
The first PHY address bit transmitted or received is the MSB of the address (bit 4). A
station management entity connected to multiple PHY entities must know the
appropriate address of each PHY
Auto-negotiation Monitor Bits
These bits are for debug only. The auto-negotiation status will be written to these
bits.
B3 B2 B1 B0
0
0
0
0
0
0
0
0
1
0
0
0
0
1
1
1
1
0
10/100Mbps Ethernet Fiber/Twisted Pair Media Converter with Local bus
0, RW
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
In IDLE state
Ability match
Acknowledge match
Acknowledge match fail
Consistency match
Consistency match fail
Parallel detects signal link ready
Parallel detects signal link ready fail
Auto-negotiation completed successfully
Remote Loop out Control
When this bit is set to 1, the received data will loop out to the
transmit channel. This is useful for bit error rate testing
Description
DM9302
Preliminary datasheet
DM9302-15-DS-P01
July 30, 2009