ncp5381a ON Semiconductor, ncp5381a Datasheet - Page 7

• Manufacturer Part Number: ncp5381a
• Description: 2/3/4 Phase Buck Controller For Vr10 And Vr11 Pentium Iv Processor Applications
• Manufacturer: ON Semiconductor

PIN DESCRIPTIONS
Pin No.
30 – 33
21, 23,
22, 24,
25, 27
26, 28
2 – 9
10
11
12
13
14
15
16
17
18
19
20
29
34
35
36
37
38
39
40
41
1
VR10/VR11
VID0–VID7
DIFFOUT
VR_RDY
VR_HOT
VR_FAN
G1 – G4
Symbol
DRVON
THPAD
COMP
DGND
ROSC
AGND
VDRP
CSxN
VREF
VCC
NTC
ILIM
VS+
VFB
CSx
VS−
EN
SS
Pull this pin high to enable controller. Pull this pin low to disable controller. Either an open−collector output
(with a pull−up resistor) or a logic gate (CMOS or totem−pole output) may be used to drive this pin. A Low to
High transition on this pin will initiate a soft start. If the Enable function is not required, this pin should be tied
directly to VREF.
Voltage ID DAC inputs.
VR select bit. Connect this pin to VTT (1.25 V) to select the VR11 DAC table. Ground this pin to select the
VR10 DAC table with VR11 type startup. Connect this pin to V
legacy VR10 type startup.
A capacitor from this pin to ground programs the soft−start time.
A resistance from this pin to ground programs the oscillator frequency. Also, this pin supplies a regulated
2.0 V which may be used with a voltage divider to the ILIM pin to set the over current shutdown threshold as
shown in the Applications Schematics.
Over current shutdown threshold. To program the shutdown threshold, connect this pin to the R
resistor divider as shown in the Applications Schematics. To disable the over current feature connect this pin
directly to the R
generated by the R
Power supply return for the analog circuits that control output voltage.
Non−inverting input to the internal differential remote V
Inverting input to the internal differential remote V
Output of the differential remote sense amplifier.
Output of the error amplifier.
Error amplifier inverting input. Connect a resistor from this pin to DIFFOUT. The value of this resistor and the
amount of current from the droop resistor (R
load.
Current signal output for Adaptive Voltage Positioning (AVP). The voltage of this pin minus 1.3 V is
proportional to the output current. Connect a resistor from this pin to V
into the feedback resistor (R
Inverting input to current sense amplifier #x, x = 1, 2, 3, 4.
Non−inverting input to current sense amplifier #x, x = 1, 2, 3, 4.
Gate Driver enable output. This pin produces a logic HIGH to enable gate drivers and a logic LOW to disable
gate drivers and has an internal 70 kW to ground.
PWM control signal outputs to gate drivers.
Voltage reference pin. This pin may be used to implement remote NTC temperature sensing as shown in the
Applications Schematic.
Power supply return for the digital circuits. Connect to AGND.
Power for the internal control circuits.
Voltage Regulator Ready (PowerGood) output. Open drain type output with internal delays that will transition
High when V
and Low when V
mV until V
Remote temperature sense connection. Connect an NTC thermistor from this pin to GND and a resistor from
this pin to V
Open drain type of output that will be low impedance when the voltage at the NTC pin is above 1.416 V.
This pin will transition to a high impedance state when the voltage at the NTC pin decreases below 1.176 V.
Open drain type of output that will be low impedance when the voltage at the NTC pin is above 1.086 V.
This pin will transition to a high impedance state when the voltage at the NTC pin decreases below 0.846 V.
Copper pad on the bottom of the IC for heatsinking. This pin should be connected to the ground plane under
the IC.
CC
REF
CORE
is removed.
. As the NTC’s temperature increases the voltage on this pin will decrease.
OSC
CORE
is higher than 300 mV below DAC, Low when V
OSC
pin. To guarantee correct operation, this pin should only be connected to the voltage
is higher than DAC+185 mV. This output is latched Low if V
pin – do not connect this pin to any externally generated voltages.
FB
http://onsemi.com
) to produce an output voltage droop. Leave this pin open for no AVP.
7
DRP
Description
) will set the amount of output voltage droop (AVP) during
CORE
CORE
sense amplifier.
sense amplifier.
REF
(4 V) to select VR10 DAC table with
CORE
FB
is lower than 380 mV below DAC,
to set the amount of AVP current
CORE
exceeds DAC+185
OSC
pin via a