ncp5381a ON Semiconductor, ncp5381a Datasheet - Page 25

• Manufacturer Part Number: ncp5381a
• Description: 2/3/4 Phase Buck Controller For Vr10 And Vr11 Pentium Iv Processor Applications
• Manufacturer: ON Semiconductor

PWM Comparators with Hysteresis
output signal at their noninverting input. Each comparator
receives one of the triangle waves offset by 1.3 V at it’s
inverting input. The output of the comparator generates the
PWM outputs G1, G2, G3, and G4.
on the valley of the triangle waveform, with steady state
duty cycle calculated by V
both high and low comparator output transitions shift phase
to the points where the error amplifier output intersects the
down and up ramp of the triangle wave.
Undervoltage Lockout
During powerup, the input voltage to the controller is
monitored, and the PWM outputs and the soft−start circuit
are disabled until the input voltage exceeds the threshold
voltage of the UVLO comparator. The UVLO comparator
incorporates hysteresis to avoid chattering, since VCC is
likely to decrease as soon as the converter initiates
soft−start.
Overcurrent Shutdown
within the IC. A comparator and latch makeup this
function. The inverting input of the comparator is
connected to the ILIM pin. The voltage at this pin sets the
maximum output current the converter can produce. The
ROSC pin provides a convenient and accurate reference
voltage from which a resistor divider can create the
overcurrent setpoint voltage. Although not actually
disabled, tying the ILIM pin directly to the ROSC pin sets
the limit above useful levels – effectively disabling
overcurrent shutdown. The comparator noninverting input
is the summed current information from the current sense
amplifiers. The overcurrent latch is set when the current
Four PWM comparators receive the error amplifier
During steady state operation, the duty cycle will center
An undervoltage lockout (UVLO) senses the VCC input.
A programmable overcurrent function is incorporated
PROTECTION FEATURES
out
/V
in
2.4
2.2
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
. During a transient event,
Figure 8. Typical VR10 Soft−Start Sequence to Vcore = 1.3 V
0
0
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information exceeds the voltage at the ILIM pin. The
outputs are immediately disabled, the VR_RDY and
DRVON pins are pulled low, and the soft−start is pulled
low. The outputs will remain disabled until the V
is removed and re−applied, or the ENABLE input is
brought low and then high.
Overvoltage Protection and Power Good Monitor
normal operation, if the voltage at the DIFFOUT pin
exceeds 1.3 V, the VR_RDY pin goes low, the DRVON
signal remains high, the PWM outputs are set low. The
outputs will remain disabled until the V
removed and reapplied. During normal operation, if the
output voltage falls more than 300 mV below the DAC
setting, the VR_RDY pin will be set low until the output
rises.
Soft−Start
programmable soft−start. The soft−start circuit works by
controlling the ramp−up of the DAC voltage during
powerup. The initial soft−start pin voltage is 0 V. The
soft−start circuitry clamps the DAC input of the Remote
Sense Amplifier to the SS pin voltage until the SS pin
voltage exceeds the DAC setting minus VID offset. The
soft−start pin is pulled to 0 V if there is an overcurrent
shutdown, if the ENABLE pin is low, if V
UVLO threshold, or if an overvoltage condition exists.
and VR11. VR10 mode simply ramps Vcore from 0 V
directly to the DAC setting at the rate set by the capacitor
connected to the SS pin. The VR11 mode ramps Vcore to
1.1 V at the SS capacitor charge rate, pauses at 1.1 V for
170 ms, reads the VID pins to determine the DAC setting,
then ramps Vcore to the final DAC setting at the
Dynamic VID slew rate of 7.3 mV/ms. Typical VR10 and
VR11 soft−start sequences are shown in the following
graphs.
TIME
An output voltage monitor is incorporated. During
The
There are two possible soft−start modes: Legacy VR10
NCP5381A
Vcore Voltage
SS Pin Voltage
VID Setting
incorporates
an
CC
CC
is below the
CC
voltage is
externally
voltage