s-8261aajmd Seiko Instruments Inc., s-8261aajmd Datasheet - Page 15

• Manufacturer Part Number: s-8261aajmd
• Description: Battery Protection Ic For Single-cell Pack
• Manufacturer: Seiko Instruments Inc.

Rev.4.4
Test Circuits
Caution Unless otherwise specified, the output voltage levels “H” and “L” at CO pin (V
(1) Test Condition 1, Test Circuit 1
(2) Test Condition 2, Test Circuit 2
(3) Test Condition 3, Test Circuit 2
(4) Test Condition 4, Test Circuit 2
(5) Test Condition 5, Test Circuit 2
(Overcharge Detection Voltage, Overcharge Hysteresis Voltage)
(Overdischarge Detection Voltage, Overdischarge Hysteresis Voltage)
(Overcurrent 1 Detection Voltage, Overcurrent 2 Detection Voltage, Load Short-Circuiting Detection Voltage)
(Charger Detection Voltage, Abnormal Charge Current Detection Voltage)
(Normal Operation Current Consumption, Power-Down Current Consumption, Overdischarge Current Consumption)
The overcharge detection voltage (V
to “L” when the voltage V1 is gradually increased from the starting condition of V1 = 3.5 V.
hysteresis voltage (V
voltage between VDD and VSS at which V
The overdischarge detection voltage (V
“H” to “L” when the voltage V1 is gradually decreased from the starting condition of V1 = 3.5 V and V2 = 0 V. The
overdischarge hysteresis voltage (V
(V
increased.
The overcurrent 1 detection voltage (V
changing V
time when the voltage V2 is increased rapidly (within 10 µs) from the starting condition V1 = 3.5 V and V2 = 0 V.
The overcurrent 2 detection voltage (V
changing V
time when the voltage V2 is increased rapidly (within 10 µs) from the starting condition V1 = 3.5 V and V2 = 0 V.
The load short-circuiting detection voltage (V
for changing V
detection delay time when the voltage V2 is increased rapidly (within 10 µs) from the starting condition V1 = 3.5 V and
V2 = 0 V.
The charger detection voltage (V
when the voltage V2 is gradually decreased from 0 V after the voltage V1 is gradually increased from the starting
condition of V1 = 1.8 V and V2 = 0 V until the voltage V1 becomes V1 = V
The charger detection voltage can be measured only in the product whose overdischarge hysteresis V
Set V1 = 3.5 V and V2 = 0 V. Decrease V2 from 0 V gradually. The voltage between VM and VSS when V
from “H” to “L” is the abnormal charge current detection voltage. The abnormal charge current detection voltage has
the same value as the charger detection voltage (V
For products with power-down function
The operating current consumption (I
V1 = 3.5 V and V2 = 0 V (Normal condition).
The power-down current consumption (I
of V1 = V2 = 1.5 V (Overdischarge condition).
For products without power-down function
The operating current consumption (I
V1 = 3.5 V and V2 = 0 V (Normal condition).
The Overdischarge current consumption (I
conditions of V1 = V2 = 1.5 V (Overdischarge condition).
DL
_00
) and the voltage between VDD and VSS at which V
judged by the threshold voltage (1.0 V) of the N-channel FET. Judge the CO pin level with respect to
V
VM
DO
DO
and the DO pin level with respect to V
from “H” to “L” lies between the minimum and the maximum value of the overcurrent 1 detection delay
from “H” to “L” lies between the minimum and the maximum value of the overcurrent 2 detection delay
DO
from “H” to “L” lies between the minimum and the maximum value of the load short-circuiting
HC
) is then defined as the difference between the overcharge detection voltage (V
CHA
HD
) is defined as the voltage between VM and VSS at which V
CU
OPE
OPE
) is then defined as the difference between the overdischarge detection voltage
) is defined as the voltage between VDD and VSS at which V
BATTERY PROTECTION IC FOR SINGLE-CELL PACK
PDN
DL
IOV1
IOV2
) is the current that flows through the VDD pin (I
) is the current that flows through the VDD pin (I
) is defined as the voltage between VDD and VSS at which V
CO
Seiko Instruments Inc.
) is the current that flows through the VDD pin (I
) is defined as the voltage between VM and VSS whose delay time for
) is defined as the voltage between VM and VSS whose delay time for
OPED
goes from “L” to “H” when the voltage V1 is gradually decreased.
SHORT
) is the current that flows through the VDD pin (I
) is defined as the voltage between VM and VSS whose delay time
CHA
SS
.
).
DO
goes from “L” to “H” when the voltage V1 is gradually
DL
+ (V
HD
/ 2).
DD
DD
) under the set conditions of
) under the set conditions of
DD
CO
) under the set conditions
) and DO pin (V
DO
S-8261 Series
goes from “L” to “H”
DD
CO
The overcharge
HD
) under the set
goes from “H”
≠ 0.
DO
CU
goes from
) and the
CO
DO
) are
goes
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