ncp1570d ON Semiconductor, ncp1570d Datasheet - Page 13

• Manufacturer Part Number: ncp1570d
• Description: Low Voltage Synchronous Buck Controller
• Manufacturer: ON Semiconductor

meet the input capacitor ripple current requirements.
Output Switch FETs
properties vary widely from manufacturer to manufacturer.
The NCP1570 system is designed assuming that n−channel
FETs will be used. The FET characteristics of most concern
are the gate charge/gate−source threshold voltage, gate
capacitance, on−resistance, current rating and the thermal
capability of the package.
the switch FET has a high gate charge, the amount of time
the FET stays in its ohmic region during the turn−on and
turn−off transitions is larger than that of a low gate charge
FET, with the result that the high gate charge FET will
consume more power. Similarly, a low on−resistance FET
will dissipate less power than will a higher on−resistance
FET at a given current. Thus, low gate charge and low
R
generated heat.
reduce power consumption. By placing a number of FETs in
parallel, the effective R
ohmic power loss. However, placing FETs in parallel
increases the gate capacitance so that switching losses
increase. As long as adding another parallel FET reduces the
ohmic power loss more than the switching losses increase,
there is some advantage to doing so. However, at some point
the law of diminishing returns will take hold, and a marginal
increase in efficiency may not be worth the board area
required to add the extra FET. Additionally, as more FETs
are used, the limited drive capability of the FET driver will
have to charge a larger gate capacitance, resulting in
increased gate voltage rise and fall times. This will affect the
amount of time the FET operates in its ohmic region and will
increase power dissipation.
dissipation in the switch FETs.
where:
practice to use the value of R
junction temperature in the calculations shown above.
P ON(BOTTOM) +
DS(ON)
I RMS(BOTTOM) + I
A total of at least 3 capacitors in parallel must be used to
Output switch FETs must be chosen carefully, since their
The onboard FET driver has a limited drive capability. If
It can be advantageous to use multiple switch FETs to
The following equations can be used to calculate power
For ohmic power losses due to R
n = number of phases.
Note that R
I RMS(TOP) +
P ON(TOP) +
will result in higher efficiency and will reduce
DS(ON)
R DS(ON)(BOTTOM) I RMS(BOTTOM) 2
( R DS(ON)(TOP) )( I RMS(TOP) ) 2
increases with temperature. It is good
2
PK
I
2
PK
DS(ON)
( number of topside FETs )
* (I PK I RIPPLE ) )
number of bottom−side FETs
* (I PK )(I RIPPLE ) ) D
DS(ON)
is reduced, thus reducing the
DS(ON)
at the FET’s maximum
:
(1 * D)
3
3
I
2
RIPPLE
I
2
RIPPLE
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13
where:
where:
Layout Considerations
D = Duty cycle.
For switching power losses:
n = number of switch FETs (either top or bottom),
C = FET gate capacitance,
V = maximum gate drive voltage (usually V
f
OSC
V
OUT
1. The fast response time of V
2. The COMP capacitor (shown below as C13)
3. The V
4. The IC should not be placed in the path of
I PEAK + I LOAD )
GND
the IC’s sensitivity to noise on the V
Fortunately, a simple RC filter, formed by the
feedback network and a small capacitor (100 pF
works well, shown below as C6) placed between
V
system practically immune to jitter. This capacitor
should be located as close as possible to the IC.
should be connected via its own path to the IC
ground. The COMP capacitor is sensitive to the
intermittent ground drops caused by switching
currents. A separate ground path will reduce the
potential for jitter.
shown below as C4) should be located as close as
possible to the IC. This capacitor’s connection to
GND must be as short as possible. The 10 Ω
resistor (shown below as R3) should be placed
close to the V
switching currents. If a ground plane is used, care
should be taken by the designer to ensure that the
IC is not located over a ground or other current
return path.
= switching frequency.
FB
and GND, filters out most noise and provides a
I RIPPLE +
CC
R4
R6
C4
R3
bypass capacitor (0.1 μF or greater,
12 V PWRGD
P D + nCV 2 (f OSC )
CC
Figure 25.
(V IN * V OUT )(V OUT )
pin.
I RIPPLE
U1
(f OSC )(L)(V IN )
2
C6
R1
+
2
I OUT
technology increases
3
C13
)
FB
I RIPPLE
line.
CC
5 V
C12
2
),