ncp1570d ON Semiconductor, ncp1570d Datasheet - Page 10

• Manufacturer Part Number: ncp1570d
• Description: Low Voltage Synchronous Buck Controller
• Manufacturer: ON Semiconductor

PWM comparator offset threshold and the artificial ramp,
the PWM comparator terminates the initial pulse.
Normal Operation
remains approximately constant as the V
maintains the regulated output voltage under steady state
conditions. Variations in supply line or output load conditions
will result in changes in duty cycle to maintain regulation.
Gate Charge Effect on Switching Times
an important effect on the switching times of the FETs. A
finite amount of time is required to charge the effective
capacitor seen at the gate of the FET. Therefore, the rise and
fall times rise linearly with increased capacitive loading.
Transient Response
transient response to any variations in input voltage and
output current. Pulse−by−pulse adjustment of duty cycle is
provided to quickly ramp the inductor current to the required
level. Since the inductor current cannot be changed
instantaneously, regulation is maintained by the output
capacitors during the time required to slew the inductor
current. For better transient response, several high
frequency and bulk output capacitors are usually used.
Overvoltage Protection
normal operation of the V
additional external components. The control loop responds
to an overvoltage condition within 200 ns, turning off the
upper MOSFET and disconnecting the regulator from its
input voltage. This results in a crowbar action to clamp the
output voltage, preventing damage to the load. The regulator
remains in this state until the overvoltage condition ceases.
Power Good
within regulation limits. Sensing for the PWRGD pin is
achieved through the V
rising, PWRGD goes high at 90% of the designed output
voltage. When the output voltage is falling, PWRGD goes
8.5 V
0.5 V
During normal operation, the duty cycle of the gate drivers
When using the onboard gate drivers, the gate charge has
The 200 ns reaction time of the control loop provides fast
Overvoltage protection is provided as a result of the
The PWRGD pin is asserted when the output voltage is
UVLO
Figure 22. Idealized Waveforms
STARTUP
FB
2
pin. When the output voltage is
control method and requires no
t
S
NORMAL OPERATION
2
control loop
V
V
V
GATE(H)
IN
COMP
FB
http://onsemi.com
10
low at 70% of the designed output voltage. PWRGD is an
open−collector output and should be externally pulled to
logic high through a resistor to limit current to no more than
20mA. Figure 23 shows the hysteretic nature of the PWRGD
pin’s operation.
Selection of the Output Capacitors
to yield optimal results. Capacitors should be chosen to
provide acceptable ripple on the regulator output voltage.
Key specifications for output capacitors are their ESR
(Equivalent Series Resistance), and ESL (Equivalent Series
Inductance). For best transient response, a combination of
low value/high frequency and bulk capacitors placed close
to the load will be required.
maximum voltage transient allowed during load transitions
has to be specified. The output capacitors must hold the
output voltage within these limits since the inductor current
can not change with the required slew rate. The output
capacitors must therefore have a very low ESL and ESR.
where:
change in output voltage due to ESR, ESL, and output
capacitor discharging or charging. Empirical data indicates
that most of the output voltage change (droop or spike
depending on the load current transition) results from the
total output capacitor ESR.
according to the formula:
These components must be selected and placed carefully
In order to determine the number of output capacitors the
The voltage change during the load current transient is:
The designer has to independently assign values for the
The maximum allowable ESR can then be determined
High
Low
PWRGD
ΔI
ΔI
Δt = load transient duration time;
ESL = Maximum allowable ESL including capacitors,
ESR = Maximum allowable ESR including capacitors
t
TR
DV OUT + DI OUT
OUT
OUT
= output voltage transient response time.
/ Δt = load current slew rate;
= load transient;
circuit traces, and vias;
and circuit traces;
Figure 23. PWRGD Assertion
ESL
Designed V
70%
Dt
Percent of
) ESR )
90%
OUT
C OUT
t TR
V
OUT