ncp1570d ON Semiconductor, ncp1570d Datasheet
ncp1570d
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ncp1570d Summary of contents
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... PIN CONNECTIONS AND MARKING DIAGRAM PWRGD PGDELAY COMP A = Assembly Location WL Wafer Lot YY Year WW Work Week ORDERING INFORMATION Device Package NCP1570D SO−8 NCP1570DR2 SO− GND V FB GATE(L) GATE(H) Shipping 98 Units/Rail 2500 Tape & Reel Publication Order Number NCP1570/D ...
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V PWRGD V LOGIC 0.1 μ PWRGD NCP1570 PGDELAY GATE(L) COMP GATE(H) C12 0.01 μF C13 0.1 μF MAXIMUM RATINGS* Operating Junction Temperature Storage Temperature Range ESD Susceptibility (Human Body Model) ESD Susceptibility ...
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ELECTRICAL CHARACTERISTICS C = 0.01 μ 0.1 μF; unless otherwise specified.) PGDELAY COMP Characteristic Error Amplifier V Bias Current FB COMP Source Current COMP Sink Current Reference Voltage COMP Max Voltage COMP Min Voltage COMP Fault Discharge Current ...
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ELECTRICAL CHARACTERISTICS (continued 0.01 μ 0.1 μF; unless otherwise specified.) PGDELAY COMP Characteristic PWM Comparator PWM Comparator Offset Ramp Max Duty Cycle Artificial Ramp Transient Response V Input Range FB Oscillator Switching Frequency General Electrical Specifications ...
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UVLO COMP V − − + 8.5 V/7.5 V − 0.25 V − GND Error Amp V − 0.985 V − COMP 0.525 V − + Σ Art Ramp 80%, 200 kHz PGDELAY ...
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TYPICAL PERFORMANCE CHARACTERISTICS Temperature (°C) Figure 3. Supply Current vs. Temperature 988 986 984 982 Temperature (°C) Figure 5. Reference Voltage vs. Temperature 520 516 512 ...
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TYPICAL PERFORMANCE CHARACTERISTICS 0.55 0.50 0.45 0.40 0.35 0.30 0.25 0. Temperature (°C) Figure 9. V Bias Current vs. Temperature FB 3.5 3.0 COMP Maximum 2.5 Voltage 2.0 1.5 COMP Fault 1.0 Threshold Voltage 0.5 0 ...
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TYPICAL PERFORMANCE CHARACTERISTICS 1000 Turn−On Threshold, 900 800 700 600 Temperature (°C) Figure 15. Power Good Thresholds vs. Temperature 11.9 11.8 11.7 11.6 11.5 11.4 11 Temperature (°C) Figure 17. PGOOD Delay ...
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THEORY OF OPERATION The NCP1570 is a simple, synchronous, fixed−frequency, low−voltage buck controller using the V provides a programmable−delay Power Good function to indicate when the output voltage is out of regulation Control Method 2 The V control ...
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PWM comparator offset threshold and the artificial ramp, the PWM comparator terminates the initial pulse. 8.5 V 0.5 V UVLO STARTUP NORMAL OPERATION t S Figure 22. Idealized Waveforms Normal Operation During normal operation, the duty cycle of the gate ...
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DV ESR ESR MAX + DI OUT where: = change in output voltage due to ESR (assigned ΔV ESR by the designer) Once the maximum allowable ESR is determined, the number of output capacitors can be found by using the ...
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This equation identifies the value of inductor that will provide the full rated switch current as inductor ripple current, and will usually result in inefficient system operation. The system will sink current away from the load during some portion of ...
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A total of at least 3 capacitors in parallel must be used to meet the input capacitor ripple current requirements. Output Switch FETs Output switch FETs must be chosen carefully, since their properties vary widely from manufacturer to manufacturer. The ...
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... Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Fax: 303− ...