ncp1231d65r2g ON Semiconductor, ncp1231d65r2g Datasheet - Page 14

• Manufacturer Part Number: ncp1231d65r2g
• Description: Lowstandby Power High Performance Pwm Controller
• Manufacturer: ON Semiconductor

NCP1231 confirms that the low output power condition is
present, and the internal SW1 opens. After the NCP1231
confirms that it is in a low power mode, versus a load
transient, the PFC_Vcc signal output is shuts down. While
the NCP1231 is in the skip mode the FB pin will move
around the 750 mV threshold level, with approximately 100
mVpïp of hysteresis on the skip comparator, at a period
which depends upon the (light) loading of the power supply
and its various time constants. Since this ripple amplitude
superimposed over the FB pin is lower than the second
threshold (1.25 volt), the PFC_Vcc comparator output stays
high (PFC_Vcc output Pin 1 is low).
and the feedback voltage rises above the 1.25 volts
threshold, the NCP1231 exits the skip mode, and returns to
normal operation.
Leaving standby (Skip Mode)
reference (leaving standby) the skip cycle activity stops and
SW1 immediately closes and restarts the PFC, there is no
delay in turning on SW1 under these conditions.
Current Sense
the current sense input is internally clamped to 1 V, so the
sense resister is determined by Rsense = 1 V/Ipk maximum.
end of the 18k resistor is connect to the output of the internal
oscillator for ramp compensation (refer to Figure 34).
Ramp Compensation
Conduction Mode (CCM) with a dutyïcycle greater than
50%, oscillation will take place at half the switching
frequency. To eliminate this condition, Ramp Compensation
can be added to the current sense signal to cure sub harmonic
oscillations. To lower the current loop gain one typically
injects between 50 and 100% of the inductor down slope.
Max I
1.25 V
0.75 V
V
In Phase four, the output power demands have increases
When the feedback voltage rises above the 1.25 volts
The NCP1231 is a peak current mode controller, where
There is a 18k resistor connected to the CS pin, the other
In Switch Mode Power Supplies operating in Continuous
FB
P
PFC is Off
Figure 33. Skip Mode
Regulation
PFC is On
Skip + 60%
100 ms
PFC is Off
Delay
No Delay
PFC is On
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NCP1231
14
is summed internally through a 18 kW resistor to the current
sense pin. To implement ramp compensation a resistor needs
to be connected from the current sense resistor, to the current
sense pin 3.
Example:
NCP1231, at 65 kHz the dv/dt of the ramp is 130 mV/ms.
Assuming we are designing a FLYBACK converter which
has a primary inductance, Lp, of 350 mH, and the SMPS has
a +12 V output with a Np:Ns ratio of 1:0.1. The OFF time
primary current slope is given by:
when imposed on a current sense resistor (Rsense) of 0.1 W.
If we select 75% of the inductor current downslope as our
required amount of ramp compensation, then we shall inject
27 mV/ms.
divider ratio (divratio) between Rcomp and the 18 kW is
0.207. Therefore:
Leading Edge Blanking
large current spike at the beginning of the current ramp due
to the Power Switch gate to source capacitance, transformer
interwinding capacitance, and output rectifier recovery
time. To prevent prematurely turning off the PWM drive
output, a Leading Edges Blanking (LEB) (Figure 35) circuit
is place is series with the current sense input, and PWM
comparator. The LEB circuit masks the first 250 ns of the
current sense signal.
The NCP1231 provides an internal 2.3 Vpp ramp which
If we assume we are using the 65 kHz version of the
With our internal compensation being of 130 mV, the
In Switch Mode Power Supplies (SMPS) there can be a
+
ï
(V out ) V f) @
Fb/3
R comp + 18k @ divratio
L p
LEB
Ns
Np
(1 * divratio)
Figure 34.
= 371 mA/ms or 37 mV/ms
18 k
CS
Rcomp
= 4.69 kW
2.3 V
0V
Rsense