ncp1231d65r2g ON Semiconductor, ncp1231d65r2g Datasheet - Page 13

• Manufacturer Part Number: ncp1231d65r2g
• Description: Lowstandby Power High Performance Pwm Controller
• Manufacturer: ON Semiconductor

Feedback
directly to the openïcollector output of an optocoupler. The
pin is pulledïup through a 20 kW resistor to the internal Vdd
supply (6.5 volts nominal). The feedback input signal is
divided down, by a factor of three, and connected to the
negative (ï) input of the PWM comparator. The positive (+)
input to the PWM comparator is the current sense signal
(Figure 31).
the feedback signal is proportional to the output power. At
the beginning of the cycle, the power switch is turnsïon and
the current begins to increase in the primary of the
transformer, when the peak current crosses the feedback
voltage level, the PWM comparators switches from a logic
level low, to a logic level high, resetting the PWM latching
FlipïFlop, turning off the power switch until the next
oscillator clock cycle begins.
ESD protection.
Skip Mode
cycle logic (Figure 32). When the feedback voltage drops
below 25% of the maximum peak current (1 V/Rsense) the
IC prevents the current from decreasing any further and
starts to blank the output pulses. This is called the skip cycle
mode. While the controller is in the burst mode the power
transfer now depends upon the duty cycle of the pulse burst
width which reduces the average input power demand.
where:
The feedback pin has been designed to be connected
The NCP1231 is a peak current mode controller, where
2
3
The feedback pin input is clamped to a nominal 10 volt for
The feedback input is connected in parallel with the skip
V
I
R
3 = Feedback divider ratio.
pk
c
s
= Current sense resistor,
= control voltage (Feedback pin input),
= Peak primary current,
FB
2.3 Vpp
Ramp
SkipLevel + 3V @ 25% + 0.75V
20k
18 k
Vdd
V c + I pk @ R s @ 3
Figure 31.
10 V
55k
LEB
25k
ï
+
PWM
http://onsemi.com
NCP1231
13
where:
where:
the skip mode
where:
asserted into a high impedance state when a light load
condition is detected and confirmed, Figure 33 shows
typical waveforms. The first section of the waveform shows
a normal startup condition, where the output voltage is low,
as a result the feedback signal will be high asking the
controller to provide the maximum power to the output. The
second phase is under normal loading, and the output is in
regulation. The third phase is when the output power drops
below the 25% threshold (the feedback voltage drops to 0.75
volts). When this occurs, the 100 mses timer starts, and if the
conditions is still present after the time output period, the
FB
P
L
f = NCP1231 controller frequency
Eff = the power supply efficiency
During the skip mode the PFC_Vcc signal (pin 1) is
in
p
= Primary inductance
= is the power level where the NCP1231 will go into
Vdd
Vskip
+
+
1.25 V
0.75 V
Vskip
/ Vstbyïout
P in +
I pk +
I pk @ R s + 1V
R out + E out
I pk + 0.75
Fault
P in + P out
Figure 32.
+
ï
ï
+
L p @ f @ I pk 2
CS Cmp
R s @ 3
2 @ P in
P out
L p @ f
Eff
2
S is rising edge triggered
R is falling edge triggered
2
S
100 ms
R
PFC_V
Latch
Reset
CC