m29dw641f STMicroelectronics, m29dw641f Datasheet - Page 39

• Manufacturer Part Number: m29dw641f
• Description: 64 Mbit 4mb X16, Multiple Bank, Boot Block 3v Supply Flash Memory
• Manufacturer: STMicroelectronics

M29DW641F
Table 10.
1. The grey cell represent Read cycles. The other cells are Write cycles.
2. SA Protection Group Address, BA Any address in the Block, BKA Bank Address, SL Standard Protection mode Lock bit
3. Refer to
4. A Reset command must be issued to return to the Read mode.
5. The 4
6. Cycle 4 erases all Non-Volatile Modify Protection bits. Cycles 5 and 6 verify that the bits have been successfully cleared
7. A 12ms timeout is required between cycles 4 and 5.
Table 11.
Verify Lock bit
Set Standard
Protection
mode
Verify Standard
Protection
mode
Password Protection mode Lock bit
Address (PL)
Standard Protection mode Lock bit Address (SL)
Non-Volatile Modify Protection bit Address (NVMP)
Extended Block Protection bit Address (OW)
Command
Address, PL Password Protection mode Lock Bit Address, PW Password Data, PWA Password Address, RPW Password
Data Being Verified, NVMP Non-Volatile Modify Protection Bit Address, OW Extended Block Protection Bit Address, X
Don’t Care. All values in the table are in hexadecimal.
Lock bits, and a block NVMP bit). The 5
DQ0=1. If DQ0=0 in the 6
required between the 4th and the 5th cycle.
when DQ0=0. If DQ0=1 in the 6
erase command, all Non-Volatile Modify Protection bits should be programmed to prevent over erasure.
(5)
(4)
th
Bus Write cycle programs a protection bit (Extended Block Protection bit, Password, Standard Protection mode
Table 11: Protection command addresses
Block Protection commands (continued)
Protection command addresses
4
6
4
Bit
Add Data Add Data Add Data Add
555
555
555
1st
th
AA 2AA
AA 2AA
AA 2AA
cycle, the program command must be issued again and verified again. A 100µs delay is
th
cycle, the erase command must be issued again and verified again. Before issuing the
2nd
th
55
55
55
and 6
Condition
RP at V
RP at V
555
555
555
th
cycles verify that the bit has been successively programmed when
3rd
for addresses.
IH
ID
58
60
60
Bus Write Operations
BA
SL
SL
Address inputs A7-A0
4th
Data
DQ0
DQ0
68
00001010
10001010
00010010
00000010
00011010
Add
SL
(1)(2)(3)
5th
Data
48
Add
SL
Other Address Inputs
Block Protection Group
Command interface
6th
Data
DQ0
Address
X
X
X
X
Add Data
7th
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