s-24c04bphal Seiko Instruments Inc., s-24c04bphal Datasheet - Page 21

• Manufacturer Part Number: s-24c04bphal
• Description: 2-wire Cmos Serial E2prom
• Manufacturer: Seiko Instruments Inc.

4. Maximum effectiveness of write protection
5. Matching phases while E
Rev.3.0
The following conditions must be satisfied to prevent erroneous writing at power-on due to write protection.
Pulling up the WP pin to V
prohibits writing all the time regardless of the conditions of the VCC, SDA, and SCL pins.
The S-24C04BPHAL does not have a pin for resetting (the internal circuit), therefore, the E
be forcibly reset externally. If a communication interruption occurs in the E
software.
For example, even if a reset signal is input to the microprocessor, the internal circuit of the E
reset as long as the stop condition is not input to the E
same status and cannot shift to the next operation. This symptom applies to the case when only the
microprocessor is reset when the power supply voltage drops. With this status, if the power supply voltage
is restored, reset the E
The following shows this reset method.
[How to reset E
(1) Set the WP pin to high level at a time other than when the write instruction is being executed, including
(2) Adjust the phase after power-on.
The E
is outputting the acknowledge signal, 0 is output to the SDA line. In this status, the microprocessor
cannot output an instruction to the SDA line. In this case, terminate the acknowledge output operation
or read operation, and then input a start instruction. Figure 22 shows this procedure.
First, input the condition. Then transmit 9 clocks (dummy clocks) of SCL. During this time, the
microprocessor sets the SDA line to high level.
acknowledge output operation or data output, so input the start condition
input, the E
operation is then possible.
*1. After 9 clocks (dummy clocks), if the SCL clock continues to be output without a start condition
Remark It is recommended to perform the above reset using dummy clocks when the system is
during power-on or off.
_00
SDA
being input, a write operation may be started upon receipt of a stop condition. To prevent this, input
a start condition after 9 clocks (dummy clocks).
SCL
2
PROM can be reset by the start and stop instructions. When the E
initialized after the power supply voltage has been raised.
2
2
PROM is reset. To make doubly sure, input the stop condition to the E
PROM]
condition
Start
2
PROM (after matching the phase with the microprocessor) and input an instruction.
2
PROM is accessed
CC
to always enable the WP pin at the absolute maximum rated voltage or lower
1
Figure 22 Resetting E
Seiko Instruments Inc.
Dummy clock
2
8
2
PROM. In other words, the E
By this operation, the E
9
2
PROM
2-WIRE CMOS SERIAL E
condition
Start
2
*1
2
PROM is reading data “0” or
PROM, it must be reset by
. When a start condition is
2
PROM interrupts the
S-24C04BPHAL
2
PROM retains the
2
PROM. Normal
condition
2
PROM cannot
Stop
2
PROM is not
2
PROM
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