hyb18tc256160af-3.7 Infineon Technologies Corporation, hyb18tc256160af-3.7 Datasheet - Page 68

• Manufacturer Part Number: hyb18tc256160af-3.7
• Description: Consumer Dram Ddr2
• Manufacturer: Infineon Technologies Corporation

3.27
During operation the DRAM input clock frequency can
be changed under the following conditions:
•
•
In the Precharge Power-down mode the DDR2-
SDRAM has to be in Precharged Power-down mode
and idle. ODT must be already turned off and CKE must
be at a logic LOW state. After a minimum of two clock
Figure 58
Data Sheet
C K , C K
C K E
C M D
During Self-Refresh operation
DRAM is in Precharge Power-down mode and ODT
is completely turned off.
T0
Input Clock Frequency Change
tRP
tAOFD
Input Frequency Change Example during Precharge Power-Down mode
T1
N O P
T2
N O P
changing the frequency
Minimum 2 clocks
required before
T3
N O P
T4
N O P
Frequency Change
Tx
N O P
occurs here
68
Tx+1
N O P
cycles after
clock frequency can be changed. A stable new clock
frequency has to be provided, before CKE can be
changed to a HIGH logic level again. After
satisfied a DLL RESET command via EMRS(1) has to
be issued. During the following DLL re-lock period of
200 clock cycles, ODT must remain off. After the DLL-
re-lock period the DRAM is ready to operate with the
new clock frequency.
before power-down exit
Ty
N O P
Stable new clock
t
Ty+1
RP
N O P
and
HYB18TC256160AF–[3S/3.7]
tXP
t
Ty+2
AOFD
N O P
256-Mbit DDR2 SDRAM
have been satisfied the input
Ty+3
D LL
R E S E T
Functional Description
07212005-A7MT-J7NM
200 clocks
ODT is off during
DLL RESET
Rev. 1.0, 2005-07
N O P
Frequ.Ch.
t
XP
Tz
C om m and
V alid
has been