hyb18tc256160af-3.7 Infineon Technologies Corporation, hyb18tc256160af-3.7 Datasheet - Page 25

• Manufacturer Part Number: hyb18tc256160af-3.7
• Description: Consumer Dram Ddr2
• Manufacturer: Infineon Technologies Corporation

3.5
The mode register stores the data for controlling the
various operating modes of DDR2 SDRAM. It programs
CAS latency, burst length, burst sequence, test mode,
DLL reset, Write Recovery (WR) and various vendor
specific options to make DDR2 SDRAM useful for
various applications. The default value of the mode
register is not defined, therefore the mode register must
be written after power-up for proper operation. The
mode register is written by asserting low on CS, RAS,
CAS, WE, BA[1:0], while controlling the state of
address pins A[12:0]. The DDR2 SDRAM should be in
all bank precharged (idle) mode with CKE already high
prior to writing into the mode register. The mode
register set command cycle time (
complete the write operation to the mode register. The
mode register contents can be changed using the same
Table 7
Field
BA2
BA1
BA0
A13
PD
Data Sheet
Bits
16
15
14
13
12
DDR2 SDRAM Mode Register Set (MRS)
Mode Register Definition (BA[2:0] = 000B)
Type
reg. addr.
w
1)
Description
Bank Address [2]
Note: BA2 not available on 256 Mbit and 512 Mbit components
0
Bank Address [1]
0
Bank Address [0]
0
Address Bus[13]
Note: A13 is not available for 256 Mbit and x16 512 Mbit configuration
0
Active Power-Down Mode Select
0
1
B
B
B
B
B
B
t
BA2, Bank Address
BA1, Bank Address
BA0, Bank Address
A13, Address bit 13
PD, Fast exit
PD, Slow exit
MRD
) is required to
25
command and clock cycle requirements during normal
operation as long as all banks are in the precharged
state. The mode register is divided into various fields
depending on functionality. Burst length is defined by
A[2:0] with options of 4 and 8 bit burst length. Burst
address sequence type is defined by A3 and CAS
latency is defined by A[6:4]. A7 is used for test mode
and must be set to 0 for normal DRAM operation. A8 is
used for DLL reset. A[11:9] are used for write recovery
time (WR) definition for Auto-Precharge mode. With
address bit A12 two Power-Down modes can be
selected, a “standard mode” and a “low-power” Power-
Down mode, where the DLL is disabled. Address bit
A13 and all “higher” address bits have to be set to 0 for
compatibility with other DDR2 memory products with
higher memory densities.
HYB18TC256160AF–[3S/3.7]
256-Mbit DDR2 SDRAM
Functional Description
07212005-A7MT-J7NM
Rev. 1.0, 2005-07