hyb18t512161bf-33 Infineon Technologies Corporation, hyb18t512161bf-33 Datasheet - Page 84

• Manufacturer Part Number: hyb18t512161bf-33
• Description: 512-mbit X16 Gddr2 Dram
• Manufacturer: Infineon Technologies Corporation

6
Table 39
Parameter
Operating Current - One bank Active - Precharge
t
commands. Address and control inputs are switching; Databus inputs are switching.
Operating Current - One bank Active - Read - Precharge
I
CL(IDD); CKE is HIGH, CS is HIGH between valid commands. Address and control inputs are
switching; Databus inputs are switching.
Precharge Power-Down Current
All banks idle; CKE is LOW;
inputs are floating
Precharge Standby Current
All banks idle; CS is HIGH; CKE is HIGH;
switching, Data bus inputs are switching
Precharge Quiet Standby Current
All banks idle; CS is HIGH; CKE is HIGH;
stable, Data bus inputs are floating.
Active Power-Down Current
All banks open;
inputs are floating. MRS A12 bit is set to “0” (Fast Power-down Exit).
Active Power-Down Current
All banks open;
inputs are floating. MRS A12 bit is set to 1 (Slow Power-down Exit);
Active Standby Current
All banks open;
valid commands. Address inputs are switching; Data Bus inputs are switching;
Operating Current
Burst Read: All banks open; Continuous burst reads; BL = 4; AL = 0, CL = CL
t
inputs are switching; Data Bus inputs are switching;
Operating Current
Burst Write: All banks open; Continuous burst writes; BL = 4; AL = 0, CL = CL
t
inputs are switching; Data Bus inputs are switching;
Burst Refresh Current
t
valid commands, Other control and address inputs are switching, Data bus inputs are switching.
Distributed Refresh Current
t
between valid commands, Other control and address inputs are switching, Data bus inputs are
switching.
Data Sheet
CK
RAS
RAS
CK
CK
OUT
=
=
=
=
=
= 0 mA, BL = 4,
t
t
t
CK(IDD)
CK(IDD)
CK(IDD)
t
t
RAS.MAX.(IDD)
RAS.MAX(IDD)
, Refresh command every
,
, Refresh command every
Specifications and Conditions
I
t
DD
RC
t
t
t
CK
CK
CK
Measurement Conditions
=
,
.
,
t
=
=
t
=
RC(IDD)
t
RP
RP
t
t
t
t
CK(IDD)
CK(IDD)
CK(IDD)
CK
=
=
t
=
t
RP(IDD)
,
RP(IDD)
t
t
CK(IDD)
RAS
, CKE is LOW; Other control and address inputs are stable; Data bus
, CKE is LOW; Other control and address inputs are stable, Data bus
;
t
t
CK
RAS
; CKE is HIGH, CS is HIGH between valid commands. Address
=
; CKE is HIGH, CS is HIGH between valid commands. Address
=
=
t
,
RAS.MIN(IDD)
t
t
CK(IDD)
t
RC
RAS.MAX(IDD)
t
=
RFC
t
REFI
t
.
;Other control and address inputs are stable; Data bus
RC(IDD)
=
t
t
CK
CK
= 7.8 s interval, CKE is LOW and CS is HIGH
t
, CKE is HIGH, CS is HIGH between valid
RFC(IDD)
=
=
,
,
t
t
t
t
RP
CK(IDD)
CK(IDD)
RAS
=
interval, CKE is HIGH, CS is HIGH between
=
t
I
RP(IDD)
OUT
t
; Other control and address inputs are
; Other control and address inputs are
RAS.MIN(IDD)
84
= 0 mA.
; CKE is HIGH, CS is HIGH between
512-Mbit Double-Data-Rate-Two SDRAM
,
t
RCD
=
t
RCD(IDD)
HYB18T512161BF–22/25/28/33
(IDD)
(IDD)
Specifications and Conditions
, AL = 0, CL =
;
;
t
t
CK
CK
=
=
t
t
CK(IDD)
CK(IDD)
05102005-C5U8-7TLE
;
;
Rev. 1.1, 2005-08
Symbol Note
I
I
I
I
I
I
I
I
I
I
I
I
DD0
DD1
DD2P
DD2N
DD2Q
DD3P(0)
DD3P(1)
DD3N
DD4R
DD4W
DD5B
DD5D
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