hyb18t512161bf-33 Infineon Technologies Corporation, hyb18t512161bf-33 Datasheet - Page 37

• Manufacturer Part Number: hyb18t512161bf-33
• Description: 512-mbit X16 Gddr2 Dram
• Manufacturer: Infineon Technologies Corporation

3.15
After a bank has been activated, a read or write cycle
can be executed. This is accomplished by setting RAS
HIGH, CS and CAS LOW at the clock’s rising edge. WE
must also be defined at this time to determine whether
the access cycle is a read operation (WE HIGH) or a
write operation (WE LOW). The DDR2 SDRAM
provides a wide variety of fast access modes. A single
Read or Write Command will initiate a serial read or
write operation on successive clock cycles at data rates
of up to 533 Mb/sec/pin for main memory. The
boundary of the burst cycle is restricted to specific
segments of the page length. For example, the 32 Mbit
(defined by CA[11, 9:0]). In case of a 4-bit burst
operation (burst length = 4) the page length of 2048 is
divided into 512 uniquely addressable segments (4-bits
within one of the 512 segments (defined by CA[8:0])
starting with the column address supplied to the device
Figure 14
CL = 3, AL = 0, RL = 3, BL = 4
Data Sheet
I/O each). The 4-bit burst operation will occur entirely
4 I/O
4 Bank chip has a page length of 2048 bits
Read and Write Commands and Access Modes
Read Timing Example
37
during the Read or Write Command (CA[11, 9:0]). The
second, third and fourth access will also occur within
this segment, however, the burst order is a function of
the starting address, and the burst sequence.In case of
a 8-bit burst operation (burst length = 8) the page length
of 2048 is divided into 256 uniquely addressable
segments (8-bits
operation will occur entirely within one of the 256
segments (defined by CA[7:0]) beginning with the
column address supplied to the device during the Read
or Write Command (CA[11, 9:0]).A new burst access
must not interrupt the previous 4 bit burst operation in
case of BL = 4 setting. Therefore the minimum CAS to
CAS delay (
write cycles.For 8 bit burst operation (BL = 8) the
minimum CAS to CAS delay (
or write cycles.Burst interruption is allowed with 8 bit
burst operation. For details see Chapter 3.20.
512-Mbit Double-Data-Rate-Two SDRAM
t
CCD
HYB18T512161BF–22/25/28/33
) is a minimum of 2 clocks for read or
4 I/O each). The 8-bit burst
t
Functional Description
CCD
05102005-C5U8-7TLE
) is 4 clocks for read
Rev. 1.1, 2005-08