lh28f400su-lc Sharp Microelectronics of the Americas, lh28f400su-lc Datasheet - Page 17
lh28f400su-lc
Manufacturer Part Number
lh28f400su-lc
Description
512k 256k Flash Memory
Manufacturer
Sharp Microelectronics of the Americas
Datasheet
1.LH28F400SU-LC.pdf
(37 pages)
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4M (512K × 8, 256K × 16) Flash Memory
READ COMPATIBLE
CHECK IF DESIRED
STATUS REGISTER
CSR FULL STATUS
CSR FULL STATUS CHECK PROCEDURE
RETRY/ERROR
CLEAR CSRD
OPERATION
READ CSRD
WRITE D0H
COMPLETE
RECOVERY
WRITE A7H
(see above)
CSR.4, 5 =
CSR.3 =
CSR.7 =
START
1
0
1
Figure 13. Erase All Unlocked Blocks with Compatible Status Registers
1
0
0
SUCCESSFUL
SUSPEND
ERASE
V
DETECT
ERASE
PP
NO
LOW
ERASE LOOP
SUSPEND
YES
CSR Full Status Check can be done after Erase All Unlocked
Block, or after a sequence of Erasures.
Write FFH after the last operation to reset
device to read array mode.
See Command Bus Cycle notes for description of codes.
CSR.3, 4, 5 should be cleared, if set, before further attempts
are initiated.
OPERATION
OPERATION
Standby
Standby
Standby
Write
Write
Read
BUS
BUS
COMMAND
COMMAND
Unlocked
Erase All
Confirm
Blocks
D = A7H
A = X
D = D0H
A = X
Q = CSRD
Toggle CE or OE
to update CSRD
A = X
Check CSR.7
1 = WSM Ready
0 = WSM Busy
Check CSR.4, 5
1 = Erase Error
0 = Erase Successful
Both 1 = Command
Sequence Error
Check CSR.3
1 = V
0 = V
PP
PP
COMMENTS
Low Detect
OK
COMMENTS
LH28F400SU-LC
28F400SUH-LC15-11
17
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