w9425g8dh Winbond Electronics Corp America, w9425g8dh Datasheet - Page 45

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w9425g8dh

Manufacturer Part Number
w9425g8dh
Description
8m ? 4 Banks ? 8 Bits Ddr Sdram
Manufacturer
Winbond Electronics Corp America
Datasheet
11.13 Read Interrupted by Write & BST (BL = 8)
Burst Read cycle must be terminated by BST Command to avoid I/O conflict.
11.14 Read Interrupted by Precharge (BL = 8)
CAS Latency = 2
CAS Latency = 2
CAS Latency = 3
CMD
CLK
CLK
DQS
CM D
DQ
CLK
CLK
DQ S
DQ S
DQ
DQ
READ
READ
Q0
Q1
Q 0
BST
Q2
Q 1
PRE
Q3
Q 2
Q 0
Q4
CAS Latency
Q 3
Q 1
Q5
- 45 -
WRIT
Q 4
Q 2
C AS Latency
Q 5
Q 3
D0
Q 4
D1
D2
Q 5
Publication Release Date: Nov. 20
D3
D4
D5
D6
D7
Revision A4
,
2007

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