w9425g8dh Winbond Electronics Corp America, w9425g8dh Datasheet - Page 13

• Manufacturer Part Number: w9425g8dh
• Description: 8m ? 4 Banks ? 8 Bits Ddr Sdram
• Manufacturer: Winbond Electronics Corp America

7.6
When the Precharge command is used for a bank in a Burst cycle, the Burst operation is terminated.
When Burst Read cycle is interrupted by the Precharge command, read operation is disabled after
clock cycle of (CAS Latency) from the Precharge command. When the Burst Write cycle is interrupted
by the Precharge command, the input circuit is reset at the same clock cycle at which the precharge
command is issued. In this case, the DM signal must be asserted "high" during t
the invalided data to the cell array.
When the Burst Read Stop command is issued for the bank in a Burst Read cycle, the Burst Read
operation is terminated. The Burst read Stop command is not supported during a write burst operation.
Refer to the diagrams for Burst termination.
7.7
Two types of Refresh operation can be performed on the device: Auto Refresh and Self Refresh. By
repeating the Auto Refresh cycle, each bank in turn refreshed automatically. The Refresh operation
must be performed 8192 times (rows) within 64mS. The period between the Auto Refresh command
and the next command is specified by t
Self Refresh mode enters issuing the Self Refresh command (CKE asserted "low") while all banks are
in the idle state. The device is in Self Refresh mode for as long as CKE held "low". In the case of
distributed Auto Refresh commands, distributed auto refresh commands must be issued every 7.8 µS
and the last distributed Auto Refresh commands must be performed within 7.8 µS before entering the
self refresh mode. After exiting from the Self Refresh mode, the refresh operation must be performed
within 7.8 µS. In Self Refresh mode, all input/output buffers are disabled, resulting in lower power
dissipation (except CKE buffer). Refer to the diagrams for Refresh operation.
7.8
Two types of Power Down Mode can be performed on the device: Active Standby Power Down Mode
and Precharge Standby Power Down Mode.
When the device enters the Power Down Mode, all input/output buffers are disabled resulting in low
power dissipation (except CKE buffer).
Power Down Mode enter asserting CKE "low" while the device is not running a burst cycle. Taking
CKE "high" can exit this mode. When CKE goes high, a No operation command must be input at next
CLK rising edge. Refer to the diagrams for Power Down Mode.
7.9
DDR SDRAM input clock frequency can be changed under following condition:
DDR SDRAM must be in precharged power down mode with CKE at logic LOW level. After a minimum
of 2 clocks after CKE goes LOW, the clock frequency may change to any frequency between minimum
and maximum operating frequency specified for the particular speed grade. During an input clock
frequency change, CKE must be held LOW. Once the input clock frequency is changed, a stable clock
must be provided to DRAM before precharge power down mode may be exited. The DLL must be
RESET via EMRS after precharge power down exit. An additional MRS command may need to be
issued to appropriately set CL etc. After the DLL relock time, the DRAM is ready to operate with new
clock frequency.
Burst Termination
Refresh Operation
Power Down Mode
Input Clock Frequency Change during Precharge Power Down Mode
RFC
.
- 13 -
Publication Release Date: Nov. 20
WR
to prevent writing
Revision A4
,
2007