w9425g8dh Winbond Electronics Corp America, w9425g8dh Datasheet - Page 34

• Manufacturer Part Number: w9425g8dh
• Description: 8m ? 4 Banks ? 8 Bits Ddr Sdram
• Manufacturer: Winbond Electronics Corp America

f. Verified under typical conditions for qualification purposes.
g. TSOP II package devices only.
h. Only intended for operation up to 266 Mbps per pin.
i. A derating factor will be used to increase t
j. A derating factor will be used to increase t
k. Table 3 is used to increase t
m. DQS, DM, and DQ input slew rate is specified to prevent double clocking of data and preserve
0.5 V/nS as shown in Table 2. The Input slew rate is based on the lesser of the slew rates
determined by either V
rates differ, as shown in Tables 3 & 4. Input slew rate is based on the larger of AC-AC delta rise,
fall rate and DC-DC delta rise, fall rate. Input slew rate is based on the lesser of the slew rates
determined by either V
The delta rise/fall rate is calculated as:
{1/(Slew Rate1)}-{1/(slew Rate2)}
For example: If Slew Rate 1 is 0.5 V/nS and Slew Rate 2 is 0.4 V/nS, then the delta rise, fall rate is
-0.5 nS/V. Using the table given, this would result in the need for an increase in t
pS.
I/O slew rate is based on the lesser of the AC-AC slew rate and the DC-DC slew rate. The input
slew rate is based on the lesser of the slew rates determined by either V
to V
setup and hold times. Signal transitions through the DC region must be monotonic.
IL(DC)
, and similarly for rising transitions.
IH(AC)
IH(AC)
DS
to V
to V
and t
IL(AC)
IL(AC)
DH
or V
or V
in the case where the I/O slew rate is below 0.5 V/nS. The
IS
IH(DC)
DS
IH(DC)
- 34 -
and t
and t
to V
to V
IH
DH
in the case where the input slew rate is below
IL(DC)
IL(DC)
in the case where DQ, DM, and DQS slew
, similarly for rising transitions.
, similarly for rising transitions.
Publication Release Date: Nov. 20
IH(AC)
to V
DS
IL(AC)
and t
Revision A4
or V
DH
of 100
IH(DC)
,
2007