cy62256vll-70zi-70sni Cypress Semiconductor Corporation., cy62256vll-70zi-70sni Datasheet
cy62256vll-70zi-70sni
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cy62256vll-70zi-70sni Summary of contents
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... Functional Description The CY62256V family is composed of two high-performance CMOS static RAM’s organized as 32K words by 8 bits. Easy memory expansion is provided by an active LOW chip enable (CE) and active LOW output enable (OE) and three-state drivers. These devices have an automatic power-down feature, reducing the power consumption by over 99% when deselected ...
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... Product Portfolio Product Range CY62256VLL Com’l / Ind’l CY62256VLL Automotive CY62256V25LL Com’l Pin Configurations Narrow SOIC Top View ...
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Maximum Ratings (Above which the useful life may be impaired. For user guide- lines, not tested.) Storage Temperature ................................. –65°C to +150°C Ambient Temperature with Power Applied............................................. –55°C to +125°C Supply Voltage to Ground Potential (Pin 28 to Pin 14) ...
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Electrical Characteristics Over the Operating Range (continued) Parameter Description I V Operating Supply Current Automatic CE Power-down SB1 Current— TTL Inputs I Automatic CE Power-down SB2 Current — CMOS Inputs [5] Capacitance Parameter C Input Capacitance ...
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Data Retention Characteristics Parameter Description V V for Data Retention Data Retention Current CCDR [6] t Chip Deselect to Data CDR Retention Time [6] t Operation Recovery Time R Data Retention Waveform Thermal Resistance ...
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... HZWE 10. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write. ...
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Switching Waveforms [12, 13] Read Cycle No. 1 ADDRESS DATA OUT PREVIOUS DATA VALID [13, 14] Read Cycle No HIGH IMPEDANCE DATA OUT t LZCE SUPPLY CURRENT Write Cycle No. 1 (WE Controlled) ...
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Switching Waveforms (continued) Write Cycle No. 2 (CE Controlled) ADDRESS CE WE DATA I/O Write Cycle No. 3 (WE Controlled, OE LOW) ADDRESS DATA I/O NOTE 17 Notes: 14. Address valid prior to or coincident with ...
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Typical DC and AC Characteristics NORMALIZED SUPPLY CURRENT vs. SUPPLY VOLTAGE 1.8 1.6 1.4 1.2 1.0 0 25GC 0.6 A 0.4 0.2 SUPPLY VOLTAGE (V) NORMALIZED ACCESS TIME vs. SUPPLY VOLTAGE 2.5 2.0 1 25GC A ...
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... H L Data Out Data High-Z Ordering Information Speed (ns) Ordering Code 70 CY62256VLL-70SNC CY62256VLL-70ZC CY62256VLL-70ZI CY62256VLL -70SNI CY62256VLL-70ZRI CY62256VLL-70SNE CY62256VLL-70ZE CY62256VLL-70ZRE 100 CY62256V25LL-100ZC Document #: 38-05057 Rev. *D (continued) 600 800 1000 Inputs/Outputs Deselect/Power-down Read Write Deselect, Output Disabled Package Name SN28 ...
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Package Diagrams 28-lead Thin Small Outline Package Type 1 (8 × 13.4 mm) Z28 Document #: 38-05057 Rev. *D 28-lead (300-mil) SNC (Narrow Body) SN28 CY62256V 51-85092-*B 51-85071-*G Page ...
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Package Diagrams (continued) 28-lead Reverse Type 1 Thin Small Outline Package (8 × 13.4 mm) ZR28 All product and company names mentioned in this document are the trademarks of their respective holders. Document #: 38-05057 Rev. *D © Cypress Semiconductor ...
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Document Title: CY62256V 256K (32K x 8) Static RAM Document Number: 38-05057 REV. ECN NO. Issue Date ** 107248 09/10/01 *A 111445 11/01/01 *B 115229 05/23/02 *C 116507 09/04/02 *D 239134 See ECN Document #: 38-05057 Rev. *D Orig. of ...