CY62256VLL-70ZRI Cypress Semiconductor Corporation., CY62256VLL-70ZRI Datasheet

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CY62256VLL-70ZRI

Manufacturer Part Number
CY62256VLL-70ZRI
Description
Manufacturer
Cypress Semiconductor Corporation.
Datasheet

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Cypress Semiconductor Corporation
Document #: 38-05057 Rev. *D
Features
• Temperature Ranges
• Speed: 70 ns and 100 ns
• Low voltage range:
• Low active power and standby power
• Easy memory expansion with CE and OE features
• TTL-compatible inputs and outputs
• Automatic power-down when deselected
• CMOS for optimum speed/power
• Package available in a standard 450-mil-wide (300-mil
Note:
1.
Logic Block Diagram
body width) 28-lead narrow SOIC, 28-lead TSOP-1, and
reverse 28-lead TSOP-1 package
— Commercial: 0°C to 70°C
— Industrial: –40°C to 85°C
— Automotive: –40°C to 125°C
— CY62256V (2.7V–3.6V)
— CY62256V25 (2.3V–2.7V)
For best practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com.
CE
WE
OE
A
A
A
A
A
A
A
A
A
10
9
8
7
6
5
4
3
2
3901 North First Street
INPUTBUFFER
512 × 512
DECODER
COLUMN
ARRA Y
Functional Description
The CY62256V family is composed of two high-performance
CMOS static RAM’s organized as 32K words by 8 bits. Easy
memory expansion is provided by an active LOW chip enable
(CE) and active LOW output enable (OE) and three-state
drivers. These devices have an automatic power-down
feature, reducing the power consumption by over 99% when
deselected.
An active LOW write enable signal (WE) controls the
writing/reading operation of the memory. When CE and WE
inputs are both LOW, data on the eight data input/output pins
(I/O
addressed by the address present on the address pins (A
through A
the device and enabling the outputs, CE and OE active LOW,
while WE remains inactive or HIGH. Under these conditions,
the contents of the location addressed by the information on
address pins are present on the eight data input/output pins.
The input/output pins remain in a high-impedance state unless
the chip is selected, outputs are enabled, and write enable
(WE) is HIGH.
POWER
DOWN
0
through I/O
256K (32K x 8) Static RAM
14
). Reading the device is accomplished by selecting
San Jose
7
) is written into the memory location
CA 95134
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
[1]
0
1
2
3
4
5
6
7
Revised June 28, 2004
CY62256V
408-943-2600
0

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CY62256VLL-70ZRI Summary of contents

Page 1

Features • Temperature Ranges — Commercial: 0°C to 70°C — Industrial: –40°C to 85°C — Automotive: –40°C to 125°C • Speed and 100 ns • Low voltage range: — CY62256V (2.7V–3.6V) — CY62256V25 (2.3V–2.7V) • Low active power ...

Page 2

... Product Portfolio Product Range CY62256VLL Com’l / Ind’l CY62256VLL Automotive CY62256V25LL Com’l Pin Configurations Narrow SOIC Top View ...

Page 3

Maximum Ratings (Above which the useful life may be impaired. For user guide- lines, not tested.) Storage Temperature ................................. –65°C to +150°C Ambient Temperature with Power Applied............................................. –55°C to +125°C Supply Voltage to Ground Potential (Pin 28 to Pin 14) ...

Page 4

Electrical Characteristics Over the Operating Range (continued) Parameter Description I V Operating Supply Current Automatic CE Power-down SB1 Current— TTL Inputs I Automatic CE Power-down SB2 Current — CMOS Inputs [5] Capacitance Parameter C Input Capacitance ...

Page 5

Data Retention Characteristics Parameter Description V V for Data Retention Data Retention Current CCDR [6] t Chip Deselect to Data CDR Retention Time [6] t Operation Recovery Time R Data Retention Waveform Thermal Resistance ...

Page 6

Switching Characteristics Over the Operating Range Parameter Read Cycle t Read Cycle Time RC t Address to Data Valid AA t Data Hold from Address Change OHA t CE LOW to Data Valid ACE t OE LOW to Data Valid ...

Page 7

Switching Waveforms [12, 13] Read Cycle No. 1 ADDRESS DATA OUT PREVIOUS DATA VALID [13, 14] Read Cycle No HIGH IMPEDANCE DATA OUT t LZCE SUPPLY CURRENT Write Cycle No. 1 (WE Controlled) ...

Page 8

Switching Waveforms (continued) Write Cycle No. 2 (CE Controlled) ADDRESS CE WE DATA I/O Write Cycle No. 3 (WE Controlled, OE LOW) ADDRESS DATA I/O NOTE 17 Notes: 14. Address valid prior to or coincident with ...

Page 9

Typical DC and AC Characteristics NORMALIZED SUPPLY CURRENT vs. SUPPLY VOLTAGE 1.8 1.6 1.4 1.2 1.0 0 25GC 0.6 A 0.4 0.2 SUPPLY VOLTAGE (V) NORMALIZED ACCESS TIME vs. SUPPLY VOLTAGE 2.5 2.0 1 25GC A ...

Page 10

... L Data Out Data High-Z Ordering Information Speed (ns) Ordering Code 70 CY62256VLL-70SNC CY62256VLL-70ZC CY62256VLL-70ZI CY62256VLL -70SNI CY62256VLL-70ZRI CY62256VLL-70SNE CY62256VLL-70ZE CY62256VLL-70ZRE 100 CY62256V25LL-100ZC Document #: 38-05057 Rev. *D (continued) 600 800 1000 Inputs/Outputs Deselect/Power-down Read Write Deselect, Output Disabled Package Name SN28 28-lead (300-mil Narrow Body) Narrow SOIC ...

Page 11

Package Diagrams 28-lead Thin Small Outline Package Type 1 (8 × 13.4 mm) Z28 Document #: 38-05057 Rev. *D 28-lead (300-mil) SNC (Narrow Body) SN28 CY62256V 51-85092-*B 51-85071-*G Page ...

Page 12

Package Diagrams (continued) 28-lead Reverse Type 1 Thin Small Outline Package (8 × 13.4 mm) ZR28 All product and company names mentioned in this document are the trademarks of their respective holders. Document #: 38-05057 Rev. *D © Cypress Semiconductor ...

Page 13

Document Title: CY62256V 256K (32K x 8) Static RAM Document Number: 38-05057 REV. ECN NO. Issue Date ** 107248 09/10/01 *A 111445 11/01/01 *B 115229 05/23/02 *C 116507 09/04/02 *D 239134 See ECN Document #: 38-05057 Rev. *D Orig. of ...

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