m24128-b STMicroelectronics, m24128-b Datasheet - Page 5

• Manufacturer Part Number: m24128-b
• Description: 256/128 Kbit Serial I??c Bus Eeprom With Three Chip Enable Lines
• Manufacturer: STMicroelectronics

Table 3. Device Select Code
Note: 1. The most significant bit, b7, is sent first.
Up to eight memory devices can be connected on
a single I
code on its Chip Enable inputs. When the Device
Select Code is received on the SDA bus, the mem-
ory only responds if the Chip Select Code is the
same as the pattern applied to its Chip Enable
pins.
The 8
and ‘0’ for write operations. If a match occurs on
the Device Select Code, the corresponding mem-
ory gives an acknowledgment on the SDA bus dur-
ing the 9
the Device Select Code, it deselects itself from the
bus, and goes into stand-by mode.
There are two modes both for read and write.
These are summarized in Table 6 and described
later. A communication between the master and
the slave is ended with a STOP condition.
Each data byte in the memory has a 16-bit (two
byte wide) address. The Most Significant Byte (Ta-
ble 4) is sent first, followed by the Least significant
Byte (Table 5). Bits b15 to b0 form the address of
the byte in memory. Bit b15 is treated as a Don’t
Care bit on the M24256-B memory. Bits b15 and
b14 are treated as Don’t Care bits on the M24128-
B memory.
Write Operations
Following a START condition the master sends a
Device Select Code with the RW bit set to ’0’, as
shown in Table 6. The memory acknowledges this,
and waits for two address bytes. The memory re-
Table 6. Operating Modes
Note: 1. X =
Device Select Code
Current Address Read
Random Address Read
Sequential Read
Byte Write
Page Write
th
bit is the RW bit. This is set to ‘1’ for read
th
2
C bus. Each one is given a unique 3-bit
V
bit time. If the memory does not match
Mode
IH
or V
IL
.
b7
1
RW bit
Device Type Identifier
1
1
0
1
1
0
0
b6
0
WC
V
V
b5
X
X
X
X
1
IL
IL
1
Data Bytes
Table 4. Most Significant Byte
Note: 1. b15 is treated as Don’t Care on the M24256-B series.
Table 5. Least Significant Byte
sponds to each address byte with an acknowledge
bit, and then waits for the data byte.
Writing to the memory may be inhibited if the WC
input pin is taken high. Any write command with
WC=1 (during a period of time from the START
condition until the end of the two address bytes)
will not modify the memory contents, and the ac-
companying data bytes will not be acknowledged,
as shown in Figure 5.
Byte Write
In the Byte Write mode, after the Device Select
Code and the address bytes, the master sends
one data byte. If the addressed location is write
protected by the WC pin, the memory replies with
a NoAck, and the location is not modified. If, in-
stead, the WC pin has been held at 0, as shown in
Figure 6, the memory replies with an Ack. The
master terminates the transfer by generating a
STOP condition.
Page Write
The Page Write mode allows up to 64 bytes to be
written in a single write cycle, provided that they
are all located in the same ’row’ in the memory:
b4
b15
b7
0
1
1
1
64
1
b15 and b14 are Don’t Care on the M24128-B series.
b14
b6
START, Device Select, RW = ‘1’
START, Device Select, RW = ‘0’, Address
reSTART, Device Select, RW = ‘1’
Similar to Current or Random Address Read
START, Device Select, RW = ‘0’
START, Device Select, RW = ‘0’
E2
b3
b13
b5
Chip Enable
b12
b4
Initial Sequence
E1
b2
M24256-B, M24128-B
b11
b3
E0
b10
b2
b1
b9
b1
RW
RW
b0
b8
b0
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