at88rf256-12 ATMEL Corporation, at88rf256-12 Datasheet - Page 6

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at88rf256-12

Manufacturer Part Number
at88rf256-12
Description
125 Khz Rfid Transponder Chip
Manufacturer
ATMEL Corporation
Datasheet
Data Transmission Protocol (Bit rate equals 16 clocks per bit)
Data Reception Protocol
Two rates for data and/or commands received by the chip
are supported. Data is received at either 2x or 4x the trans-
mission rate, selectable by using the RCLK_GEN option
bit. Over the range of possible TCLK_GEN values, this
translates into a range of 32 cycles/bit to 4096.
All data and commands received by the chip must be
Manchester encoded by the reader/writer. The part is capa-
ble of detecting incoming data at amplitude changes
(modulation depth) greater than 15%. At deep modulation
levels, the chip may reset at far field during modulation
intervals.
There is no delay between the last bit of the command
transmitted by the reader/writer to the chip and the first
data bit sent on a write command. After a read command,
the chip will wait one receive bit time to ensure that there is
no more modulation, and will then commence with the
transmission of the read data.
NRZ DATA
MANCHESTER
(BI-PHASE)
MILLER
PSK2
MANCHESTER
SUBCARRIER
BIT
5
1
BIT
4
0
For incoming modulation, a bit time, in which there is low
field strength in the first half of the bit time and high field
strength in the second half, is interpreted as a logic 0. High
field strength in the first half of the bit time, and low field
strength in the second half is interpreted as a logic 1.
Reset Voltage
The chip includes a precision voltage reference to ensure
that all write commands are only performed when the
power supply voltage on the chip is above a required level
of 2.0V. ID reads and the “read” and “disable” commands
will take place regardless of voltage (above a minimal POR
level), which will result in correct information in most cases.
Data transmitted at the lowest voltages may not be valid;
therefore, some sort of error detection and/or correction
(multiple reads, parity, hamming code, etc.) must be imple-
mented by the system.
BIT
3
1
BIT
2
1
BIT
1
0
BIT
0
0
6

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