at25128b ATMEL Corporation, at25128b Datasheet - Page 8

• Manufacturer Part Number: at25128b
• Description: Spi Serial Eeproms
• Manufacturer: ATMEL Corporation

3.
8
Functional Description
The AT25128B/256B is designed to interface directly with the synchronous serial peripheral interface (SPI) of the 6800
type series of microcontrollers.
The AT25128B/256B utilizes an 8-bit instruction register. The list of instructions and their operation codes are
contained in Figure 6. All instructions, addresses, and data are transferred with the MSB first and start with a high-to-
low
Table 5.
WRITE ENABLE (WREN): The device will power-up in the write disable state when V
WRITE DISABLE (WRDI): To protect the device against inadvertent writes, the Write Disable instruction disables all
READ STATUS REGISTER (RDSR): The Read Status Register instruction provides access to the status register. The
Table 6.
Table 7.
AT25128B/256B [Preliminary]
WREN
WRDI
RDSR
WRSR
READ
WRITE
Bit 0 (
Bit 1 (WEN)
Bit 2 (BP0)
Bit 3 (BP1)
Bits 4 – 6 are 0s when device is not an internal write cycle.
Bit 7 (WPEN)
Bits 0 – 7 are “1”s during an internal write cycle.
Instruction Name
WPEN
Bit 7
transition.
)
Bit
Instruction Set for the AT25128B/256B
Status Register Format
Read Status Register Bit Definition
instructions must therefore be preceded by a Write Enable instruction.
programming modes. The WRDI instruction is independent of the status of the
Ready/Busy and Write Enable status of the device can be determined by the RDSR instruction.
Similarly, the Block Write Protection bits indicate the extent of protection employed. These bits are
set by using the WRSR instruction.
Bit 6
X
Bit 0 = “0” (
Bit 0 = “1” indicates the write cycle is in progress.
Bit 1 = 0 indicates the device is not write enabled.
Bit 1 = “1” indicates the device is write enabled.
See
See
See Table 9
Instruction Format
0000 X 010
0000 X110
0000 X100
0000 X101
0000 X001
0000 X011
Table 8
Table 8
Bit 5
X
on
on
on
) indicates the device is ready.
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page 9
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Set Write Enable Latch
Reset Write Enable Register
Read Status Register
Write Status Register
Read Data from Memory Array
Write Data to Memory Array
.
.
.
Bit 4
X
Bit 3
BP1
Definition
Operation
Bit 2
BP0
CC
is applied. All programming
WEN
Bit 1
pin.
8593A–SEEPR–01/09
Bit 0