at25128b ATMEL Corporation, at25128b Datasheet - Page 10

• Manufacturer Part Number: at25128b
• Description: Spi Serial Eeproms
• Manufacturer: ATMEL Corporation

4.
10
A Write Instruction requires the following sequence. After the
code is transmitted via the SI line followed by the byte address and the data (D7 - D0) to be programmed
Programming will start after the
SCK low time immediately after clocking in the D0 (LSB) data bit.
The Ready/Busy status of the device can be determined by initiating a Read Status Register (RDSR) Instruction. If Bit 0
= 1, the Write cycle is still in progress. If Bit 0 = 0, the Write cycle has ended. Only the Read Status Register instruction
is enabled during the Write programming cycle.
The AT25128B/256B is capable of a 64-byte Page Write operation. After each byte of data is received, the six low
order address bits are internally incremented by one; the high order bits of the address will remain constant. If more
than 64 bytes of data are transmitted, the address counter will roll over and the previously written data will be
overwritten. The AT25128B/256B is automatically returned to the write disable state at the completion of a Write cycle.
NOTE: If the device is not write enabled (WREN), the device will ignore the Write instruction and will return to the
Table 10.
Timing Diagram (for SPI Mode 0 (0,0)
Figure 4.
AT25128B/256B [Preliminary]
SCK
CS
SO
SI
Don’t Care Bits
V
V
V
V
V
V
V
V
O H
O L
Address
IH
IH
IH
IL
IL
IL
t
standby state, when
communication.
C SS
A
HI-Z
N
Address Key
Synchronous Data Timing
t
SU
AT25128B
is brought high. A new
A
A
VALID IN
15
pin is brought high. (The Low-to-High transition of the
13
− A
− A
14
0
t
W H
t
H
AT25256B
A
falling edge is required to re-initiate the serial
14
A
t
− A
W L
15
0
line is pulled low to select the device, the Write op-
t
V
t
HO
pin must occur during the
t
C SH
8593A–SEEPR–01/09
t
D IS
t
HI-Z
(Table
C S
10).