at25128b ATMEL Corporation, at25128b Datasheet - Page 6

• Manufacturer Part Number: at25128b
• Description: Spi Serial Eeproms
• Manufacturer: ATMEL Corporation

2.
6
Note:
Serial Interface Description
MASTER:
SLAVE:
TRANSMITTER/RECEIVER: The AT25128B/256B has separate pins designated for data transmission (SO) and
MSB:
SERIAL OP-CODE:
INVALID OP-CODE:
CHIP SELECT:
HOLD:
WRITE PROTECT:
AT25128B/256B [Preliminary]
t
t
t
Endurance
HZ
DIS
WC
Symbol
1. This parameter is characterized and is not 100% tested. Contact Atmel for further information.
(1)
Output Disable Time
Write Cycle Time
5.0V, 25°C, Page Mode
to Output High Z
The device that generates the serial clock.
Because the serial clock pin (SCK) is always an input, the AT25128B/256B always operates
as a slave.
reception (SI).
The Most Significant Bit (MSB) is the first bit transmitted and received.
After the device is selected with
the op-code that defines the operations to be performed.
If an invalid op-code is received, no data will be shifted into the AT25128B/256B, and the
serial output pin (SO) will remain in a high impedance state until the falling edge of
detected again. This will reinitialize the serial communication.
The AT25128B/256B is selected when the
will not be accepted via the SI pin, and the serial output pin (SO) will remain in a high
impedance state.
The
device is selected and a serial sequence is underway,
communication with the master device without resetting the serial sequence. To pause, the
to the SI pin will be ignored while the SO pin is in the high impedance state.
The write protect pin (
inhibited.
internal write cycle has already been initiated,
operation to the status register. The
status register is “0”. This will allow the user to install the AT25128B/256B in a system with the
enabled when the WPEN bit is set to “1”.
Parameter
pin tied to ground and still be able to write to the status register. All
pin is brought low and WPEN bit is “1”, all write operations to the status register are
pin must be brought low while the SCK pin is low. To resume serial communication, the
pin is brought high while the SCK pin is low (SCK may still toggle during
pin is used in conjunction with the
going low while
) will allow normal read/write operations when held high. When the
Voltage
4.5−5.5
2.5−5.5
1.8−5.5
4.5−5.5
2.5−5.5
1.8−5.5
4.5−5.5
2.5−5.5
1.8−5.5
is still low will interrupt a write to the status register. If the
going low, the first byte will be received. This byte contains
pin function is blocked when the WPEN bit in the
pin is low. When the device is not selected, data
pin to select the AT25128B/256B. When the
Min
1M
going low will have no effect on any write
can be used to pause the serial
Max
100
100
25
50
25
50
5
5
5
pin functions are
8593A–SEEPR–01/09
Write Cycles
Units
ms
ns
ns
). Inputs
is