at25df161 ATMEL Corporation, at25df161 Datasheet - Page 39

• Manufacturer Part Number: at25df161
• Description: 16-megabit 2.7-volt Minimum Spi Serial Flash Memory
• Manufacturer: ATMEL Corporation

11.1.7
11.1.8
11.1.9
11.1.10
Figure 11-1. Read Status Register
3687B–DFLASH–11/08
SLE Bit
PS Bit
ES Bit
RDY/BSY Bit
SCK
SO
CS
SI
MSB
HIGH-IMPEDANCE
0
The RSTE bit will retain its state as long as power is applied to the device. Once set to the logi-
cal “1” state, the RSTE bit will remain in that state until it is modified using the Write Status
Register Byte 2 command or until the device has been power cycled. The Reset command itself
will not change the state of the RSTE bit.
The SLE bit is used to enable and disable the Sector Lockdown and Freeze Sector Lockdown
State commands. When the SLE bit is in the logical “0” state (the default state after power-up),
the Sector Lockdown and Freeze Sector Lockdown commands are disabled. If the Sector Lock-
down and Freeze Sector Lockdown commands are disabled, then any attempts to issue the
commands will be ignored. This provides a safeguard for these commands against accidental or
erroneous execution. When the SLE bit is in the logical “1” state, the Sector Lockdown and
Freeze Sector Lockdown State commands are enabled.
Unlike the WEL bit, the SLE bit does not automatically reset after certain device operations.
Therefore, once set, the SLE bit will remain in the logical “1” state until it is modified using the
Write Status Register Byte 2 command or until the device has been power cycled. The Reset
command has no effect on the SLE bit.
If the Freeze Sector Lockdown State command has been issued, then the SLE bit will be perma-
nently reset in the logical “0” state to indicate that the Sector Lockdown command has been
disabled.
The PS bit indicates whether or not a sector is in the Program Suspend state.
The ES bit indicates whether or not a sector is in the Erase Suspend state.
The RDY/BSY bit is used to determine whether or not an internal operation, such as a program
or erase, is in progress. To poll the RDY/BSY bit to detect the completion of a program or erase
cycle, new Status Register data must be continually clocked out of the device until the state of
the RDY/BSY bit changes from a logical “1” to a logical “0”.
0
0
1
0
2
OPCODE
0
3
0
4
1
5
0
6
1
7
MSB
D
8
STATUS REGISTER
D
9
D
10 11
BYTE 1
D
D
12
D
13 14
D
D
15 16
MSB
D
STATUS REGISTER
D
17
D
18
BYTE 2
AT25DF161 [Preliminary]
D
19
D
20
D
21 22
D
D
23 24
MSB
D
STATUS REGISTER
D
25
D
26
BYTE 1
D
27
D
28 29
D
D
30
D
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