pnx8511 NXP Semiconductors, pnx8511 Datasheet - Page 18

• Manufacturer Part Number: pnx8511
• Description: Analog Companion Chip
• Manufacturer: NXP Semiconductors

Philips Semiconductors
9397 750 12612
Product data
Fig 15. Primary display pipe
HD operation mode
secondary
CBLANK
primary
V/O_E
D1
D1
H
D1-INTERFACE
D1-INTERFACE
7.1.8 PAL/NTSC/SECAM encoder
EXTRACT
EXTRACT
SYNC
SYNC
V/O_E
The PAL/NTSC/SECAM encoder accepts the YUV data and encodes it into an NTSC,
PAL or SECAM video signal. From Y, U and V data, the encoder generates
luminance, chrominance and subcarrier output signals, suitable for use as CVBS or
separate Y and C signals.
Luminance is modified in gain and in offset (offset is programmable to enable different
black level setups). In order to enable easy analog post filtering, luminance is
interpolated from a 13.5 MHz data rate to a 27 MHz data rate, providing luminance in
10-bit resolution. This filter is also used to define smoothed transients for
synchronization pulses and the blanking period. Chrominance is modified in gain
(programmable separately for U and V). The standard dependent burst is inserted
before baseband color signals are interpolated from a 6.75 MHz data rate to a
27 MHz data rate.
One of the interpolation stages can be bypassed providing a higher color bandwidth,
which can be used for Y and C output. The register bits FSC0 to FSC3 set the
subcarrier frequency. To make sure the subcarrier is locked to the line frequency, as
the standards require, the sync generator is able to reset the subcarrier generation
periodically. This feature is controlled by the PHRES (register MULTICTL, offset
0x6E) programming bits. These features are available to generate a standard
interlaced signal; they will not work in non-interlaced mode.
A crystal-stable master clock of 27 MHz, which is twice the CCIR line-locked pixel
clock of 13.5 MHz, is received from the interface clock pins. The encoder synthesizes
all necessary internal signals, color subcarrier frequency, and synchronization signals
from that clock.
For ease of analog post filtering, the signals are twice oversampled with respect to
the pixel clock before digital-to-analog conversion.
(1)
DEMUX
UP-SAMPLE
Rev. 04 – 12 January 2004
BYPASS
BYPASS
GAIN CONTROL
SYNC-RASTER
GENERATOR
SYNC-SHAPER
SYNC-INSERT
LEVEL-SHIFT
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
PNX8510/11
Analog companion chip
U/C B /P B /G-DAC
V/C R /B-DAC
Y/R-DAC
MDB649
H
V
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